Sep 26, 2008

EUROSOI 2009

The 2009 EUROSOI Workshop will be held at Chalmers University, Göteborg (Sweden) on January 19-21 2009.

The EUROSOI Workshop started as an event related to a former Coordination Action (called EUROSOI) funded by the European Commission. This Thematic Network, which includes most of the European teams working on SOI technology, will continue to exist at least until 2011, under the name of EUROSOI+, receiving more funding from the European Commission.

The EUROSOI Workshop has become an international forum to discuss the recent advances on all aspects of SOI technology: materials, devices, modeling, simulation and circuits.

EUROSOI 2008 will be organized by the Chalmers University. The Chairman is Prof Olof Engström, a recognized researcher in nanoscale semiconductor devices, including SOI technology.

The deadline for abstract submission is November 15 2008

Topics include all areas related to SOI technology, devices and circuits. The "SOI MOSFET modeling" topic is explicitly mentioned.

Göteborg is a leading conferences and event city in Europe. There is a strong joint commitment between the business community and the city council to support major events and conferences offering professionalism and excellent organizational skills.

Do not expect a very nice weather in Göteborg in January, but there are many things to see and enjoy in Göteborg.

ISPSD'09

The 21st IEEE International Symposium on Power Semiconductor Devices and ICs will take place in Barcelona (Catalonia, Spain) on June 14-18.

The deadline for abstract submission is October 24 2008.

ISPSD is the main international conference on the areas of power semiconductor devices, power integrated circuits, their hybrid technologies, and applications.

Topics include: processes, materials, CAD/Simulation, devices, power ICs, packaging and applications.

For researchers interested in compact modeling of power semiconductor devices, ISPSD is a top event to present and get to know the last results in this field. "Device & circuit simulation" is explicitly mentioned as one of the subtopic in the "CAD/Simulation" topic. Compact modeling fits very well this subject. And of course, there is a subtopic of "Modeling" in the "Device" topic.

The Conference will take place mainly at the Axa Winterthur Auditorium but some parallel sessions will be held at the NH Constanza Hotel which is just beside the Auditorium.

Certainly Barcelona is a wonderful place to have such an important event. There are many superb attractions in Barcelona: historical landmarks, the well-known modernistic buildings in Gaudi-style, the "Barri Gòtic" (middle-age downtown), the Museum of Fine Arts, or the stadium of the Barça Football Club. And one can find nice beaches very close to Barcelona. The weather in June is usually very good, warm enough to go to the beach, without been too hot.

Sep 22, 2008

Position in CMOS Compact Modelling

The IHP - Innovations for High Performance Microelectronics (Frankfurt Oder, Germany) invites applications for a position in CMOS Compact Modelling and Technology Support.

The IHP is seeking a candidate with a Master degree in Electrical Engineering or Physics. The main tasks will be:

The main tasks will be:

- SPICE compact modelling of CMOS based devices in IHPs 0.25µm and 0.13µm
technologies

- Electrical measurements and characterization on device level

- Automation of modelling and measurement procedures

- Support statistical analysis of electrical test data


The successful candidates must be highly motivated with basic knowledge in semiconductor device physics and electrical measurement and characterization.

Applicants have to send their application letter/e-mail by September 22, 2008 (if they arrive a few days later they may be considered too) including CV, copies of (scanned) certificates, and addresses of at least one referee to:

Dr. Christel Quick

IHP GmbH

Im Technologiepark 25

15236 Frankfurt (Oder)

Germany

Phone: +49 335 5625 330

Fax: +49 335 5625 666

Email: quick@ihp-microelectronics.com

The IHP is a non-profit making organization which pursues interdisciplinary application-oriented research in the fields of high performance microelectronics and communication, particularly Materials Research, Technology Research, Circuit Design and System Design.

This position offers a unique opportunity to work at the forefront of semiconductor technology in an upcoming new field. The IHP offers a challenging, multinational environment, with excellent career prospects.



Sep 4, 2008

IEEE 2009 ICMTS Call for Papers

The IEEE 2009 ICMTS has launched the final call for papers (deadline: Sept. 15, 2008). The complete Call for Papers is on their website at: http://www.see.ed.ac.uk/ICMTS. Authors are asked to submit a two or three page extended abstract in PDF file format (font-embedded) including a 500- to 1500-word summary, major figures, and data for review.

This edition will be held between March 30 – April 2, 2009, Mandalay Beach Resort, Oxnard, CA, USA, and there is a suggested topic including "Device and Circuit Modeling, Parameter Extraction", so it seems a nice opportunity to visit the USA, and California.... (no links included, because it is too well known a location)... but I include a picture of the hotel:


tempting, isn't it?

Aug 22, 2008

Post Doctoral Fellowship at UNIK (Norway), in Advanced CMOS Device Modeling

Position Description: One Post Doctoral fellowship for 18 months in the research group of Professor Tor A. Fjeldly in the area of advanced electronic device modeling, simulation and characterization.

The candidate will work at UNIK - University Graduate Center (www.unik.no)located near Oslo. UNIK is affiliated with University of Oslo (www.uio.no) and Norwegian University of Science and Technology (NTNU) (www.ntnu.no).
Terms of Employment: The salaries and terms at UNIK are in accordance with Norwegian governmental regulations. The annual salary for the post doctoral fellow is 435 000 NOK (about 81 000 USD as of mid-August 2008), including five weeks per year of paid vacation per year of actual service. Health benefits and full salary during illness are provided.

Project: The position is financed by the European Union project COMON - Compact Modelling Network, which is coordinated by Prof. Benjamin Iñiguez (Universitat Rovira i Virgili, Spain)

For a more detailed description of the project see:

http://brage.unik.no/personer/torfj/Projects/COMON/COMON_Annex.pdf

Research Topics:
• Compact modeling of nanoscale MOSFETs
• Model validation
• Parameter extraction techniques
• Model implementation

Startup and Deadline: Applicants are encouraged to apply at the earliest convenience. The deadline for the application is September 15, 2008. The startup date is flexible and can be chosen by the candidate in consultation with Professor Fjeldly. The COMON project is provisionally scheduled to start on October 1, 2008.

How to Apply: Applicants must submit official academic records for their bachelor, masters, and Ph.D. education, and a complete publication list. It is a requirement to hold a Ph.D. or an equivalent degree for being considered for this position. At least three academic references (name, position, e-mail, and telephone number) should be
included in the application.

Applicants are encouraged to submit their applications electronically to:
postmottak@unik.no and torfj@unik.no
Home-page of Prof. Fjeldly: http://brage.unik.no/personer/torfj
Office phone: +47-64844700 or +47-64844747
Otherwise, send by regular mail to:
UNIK - University Graduate Center
Attn: Tor A. Fjeldly
Instituttveien 25, P. O. Box 70
N-2027 Kjeller, Norway
Background: The candidates must have a solid background in electronics, semiconductor device physics, and mathematics. The ability to program in Matlab or other similar programming languages is also essential.
Candidate Evaluation Criteria: To evaluate the candidates, the following prioritized criteria will be used:
1) International publications (journal & conference) on relevant topics, i.e., scientific productivity and the time spent to produce the scientific work.
2) University education
• Grades: To be considered, the applicant should have mainly A or B for relevant courses and overall good grades
to demonstrate the capacity to learn new material
• The time used to complete the Bachelors, Masters, and Ph.D. university degrees should follow the normal study
time period
• Proficiency in English as documented by TOEFL, IELTS, or equivalent practical use of English.
• GRE score if available
• Completion of courses indicating relevant knowledge in
– Electronics
– Semiconductor device physics
– Mathematics
• Relevance of Ph.D. (and Masters) research topics
3) Industrial experience in electronics
4) Teaching experience
5) Females are given priority when competing with men of equal qualifications.
Description of UNIK - University Graduate Center: UNIK is a graduate educational institution for Master’s, graduate engineering and doctoral students, primarily affiliated with University of Oslo or Norwegian University of Science and Technology (NTNU), but also for continuing education students from commerce and
industry. Courses are offered in four academic fields:
• Electronics and Photonics
• Networking, Information Security, and Signal Processing for
Communications
• Cybernetics and Industrial Mathematics
• Energy and the Environment
UNIK offers courses and supervision on behalf of University of Oslo and NTNU. For more information see: www.unik.no.
Help to find a place to live: UNIK will help the chosen candidate to find a place to live near UNIK. UNIK will help the candidate and his/her family to sign up for courses in Norwegian language, if desired.

Jul 30, 2008

Papers on IEEE Trans on Electron Devices (Aug 2008)

Well, it seems that this has been a very productive issue:

Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability
Millar, C. Reid, D. Roy, G. Roy, S. Asenov, A. (link)

Analytical Threshold Voltage Model for Double-Gate MOSFETs With Localized Charges
Kang, H. Han, J.-W. Choi, Y.-K. (link)

Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs
Asenov, A. Cathignol, A. Cheng, B. McKenna, K. P. Brown, A. R. Shluger, A. L. Chanemougame, D. Rochereau, K. Ghibaudo, G. (link)

A Charge-Based Model for Long-Channel Cylindrical Surrounding-Gate MOSFETs From Intrinsic Channel to Heavily Doped Body
Liu, F. He, J. Zhang, L. Zhang, J. Hu, J. Ma, C. Chan, M. (link)

Drain Current Model Including Velocity Saturation for Symmetric Double-Gate MOSFETs
Hariharan, V. Vasi, J. Rao, V. R. (link)

A Unified Analytic Drain–Current Model for Multiple-Gate MOSFETs
Yu, B. Song, J. Yuan, Y. Lu, W.-Y. Taur, Y. (link)

A Quasi Two-Dimensional Conduction Model for Polycrystalline Silicon Thin-Film Transistor Based on Discrete Grains
Wong, M. Chow, T. Wong, C. C. Zhang, D. (link)

Simulation of the Impact of Process Variation on the Optimized 10-nm FinFET
Khan, H. R. Mamaluy, D. Vasileska, D. (link)

Investigation of the Transport Properties of Silicon Nanowires Using Deterministic and Monte Carlo Approaches to the Solution of the Boltzmann Transport Equation
Lenzi, M. Palestri, P. Gnani, E. Reggiani, S. Gnudi, A. Esseni, D. Selmi, L. Baccarani, G. (link)

A Physical Model of High Temperature 4H-SiC MOSFETs
Potbhare, S. Goldsman, N. Lelis, A. McGarrity, J. M. McLean, F. B. Habersat, D. (link)

3C-Silicon Carbide Nanowire FET: An Experimental and Theoretical Approach
Rogdakis, K. Lee, S.-Y. Bescond, M. Lee, S.-K. Bano, E. Zekentes, K. (link)

Characterization, Modeling, and Application of 10-kV SiC MOSFET
Wang, J. Zhao, T. Li, J. Huang, A. Q. Callanan, R. Husna, F. Agarwal, A. (link)

Jul 18, 2008

Nice papers (July, 2008)

No, we're not dead, but overworked... Here you have some nice papers, from various sources, including one which is unexpected...

A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET
Chung Ha Suh, Solid-State Electronics (abstract)

Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond
Jeffrey B. Johnson, Terence B. Hook, and Yoo-Mi Lee, IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 7, JULY 20 (abstract)

An Analytical Model Based on Surface Potential for a-Si:H Thin-Film Transistors
Yuan Liu, Student Member, IEEE, Ruo-he Yao, Bin Li, Member, IEEE, and Wan-Ling Deng, JOURNAL OF DISPLAY TECHNOLOGY, VOL. 4, NO. 2, JUNE 2008 (abstract)