10th IWCM Workshop Program

10th International Workshop on Compact Modeling 

January 22 (Tue), 2013 

Pacifico Yokohama, Room 419

Yokohama, Japan

Time	#	Title	Authors	Affiliation
9:00-9:10		Opening: H. J.  Mattausch (Workshop Chair)
		Power Devices   Chair: D. Navarro
9:10-9:30	1	HiSIM_HV Temperature Modeling for Multi-Geometry LDMOS: Comparison of the Temperature Flag Options	Y. Iino	Silvaco Japan
9:30-9:50	2	Analysis and Further Improvements of the Drain-Resistance Modeling in HiSIM_HV	T. Umeda et al.	Hiroshima University
9:50-10:10	3	Floating-Base Effect Modeling for IGBT Structure using Potential Modification	T. Yamamoto et al.	Denso
10:10-10:30		- Break -
		Novel FET Structures Chair: T. Nakagawa
10:30-10:50	4	Study on Dynamic Threshold Nanowire Tunnel FET	A. Zhang et al.	Peking University Shenzhen
10:50-11:10	5	A DC Model of TFETs for SPICE Simulations	L. Zhang and M. Chan	HK UST
11:10-11:30	6	A Surface Potential Based Compact Model of Organic Thin-Film Transistor for Circuit Simulation	T.K. Maiti et al.	Hiroshima University
11:30-11:40		-  Break -
		Optical and Wireless Chair: J. He
11:40-12:00	7	An Embedded Modulation of Silicon Germanium FIN-LED - A simulation study	J. Kwon et al.	Seoul National University
12:00-12:20	8	Predicting Key Parameters of Inductive Power Links	S. Raju et al.	HK UST
12:20-14:00		- Lunch Break -
		Aging and Degradation Chair: M. Miura-Mattausch
14:00-14:40	9	Invited Keynote: Interaction of Bloch Carrier and Bound State in the Reliability Modeling	Y.J. Park and S. Choi	Seoul National University
14:40-15:00	10	Development of Unified Predictive NBTI Model and its Application for Circuit Aging Simulation	C. Ma et al.	Hiroshima University, STARC
15:00-15:20	11	Effects of Nonlocal Concentration of Carriers in the Oxide for NBTI Simulation	S. Rhee et al.	Seoul National University
15:20-15:40		-  Break -
		Fabrication Variation Chair: Y. J. Park
15:40-16:00	12	Parameter Extraction for Statistical Variation of HV-MOSFETs	Y. Ueda et al.	Ricoh, STARC
16:00-16:20	13	Analysis of Gate-Length Dependence of MOSFET Random Variation by Using HiSIM-RP	S. Kumashiro et al.	Renesas Electronics
16:20-16:40	14	Random Dopant Fluctuation Effects on Double Gate Tunneling FET Performance	Y. Zhu et al.	Peking University Shenzhen
16:40-16:50		Closing: H.J. Mattausch (Workshop Chair)

IDESA Lecture

Lecture: MOSFET Modelling
J-M. Sallese; EPFL

Specific 90nm physical effects (DIBL, gate current, mobility saturation, velocity saturation). Available models and their RF performance: BSIM, EKV3, PSP. Modeling of analog and RF parameters (e.g., gm/ID, gm/gDS, CV modeling, gate leakage, etc.). Other topics include: noise modeling, distortion, breakdown effects, thermal issues and power devices, and physical layout effects (parasitics, test, maximizing gain-bandwidth, etc.). 

Location: STFC/RAL, UK; From: 14-Jan-2013 To: 18-Jan-2013

[more about IDESA Courses]

Job offer for Compact Modelling Engineer.

A job offer for compact modelling engineers, found in the web. For more information about the company, visit their website. Remember that we're not associated with them in any manner, and that we only post this as an information.

Compact Model Engineer
Reporting To: VP of Technology
Company: IO Semiconductor, Inc.
Location: San Diego, CA

Job Description and Responsibilities

• Collaborate with product development, technology development and process engineering teams on the evaluation, optimization, validation, assessment and characterization of compact device models for circuit simulation.
• Characterization and analysis of solid-state devices
• Refinement and optimization of compact models for improved analog and RF
• design efficiency and implementation on EDA platforms
• DC and RF Spice model parameter sets for typical and skewed conditions
• Device and circuit simulations
• Test structure designs for parameter extractionReports, presentations and interpretations of simulation and characterization results

Required Skills and Experience

• MS or PhD in electrical engineering, physics or equivalent
• Solid technical understanding of semiconductor device physics, device
• characterization and compact modelling for circuit simulation.
• Experience with electrical characterization, including proficiency in setting-up
• and programming measurement systems.
• Programming experience in at least one high-level, script-based language, such as
• HP Basic, Matlab or LabVIEW.
• Experience in test structure design and layout.
• Expertise in silicon-on-insulator (SOI) transistor physics and high speed device
• characterization are highly desirable.
• Experience with process and device simulation and modelling (TCAD) tools is
• desirable.
• Excellent verbal and written communication skills and a proven ability to work in
• teams.
• Excellent analytical skills
• Excellent time management and organisational skills
• A strong, hands-on individual contributor and a self-starter
• Sound communication and interpersonal skills
• Demonstrated ability to work effectively with others

[mos-ak] [on-line publications] 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

The MOS-AK/GSA Working Group, a global compact modeling standardization forum, has delivered their 5th international compact modeling workshop, organized on Dec. 12, 2012 in the time frame of the IEDM Conference in San Francisco. The event was organized at swissnex receiving full sponsorship provided by leaders in electronic design automation including Agilent Technologies and Mentor Graphics. The FP7 COMMON Project, Eurotraining, and MOSIS Services were among the workshop technical program promoters. More than 40 international academic researchers and modeling engineers attended two sessions to hear 11 technical compact modeling talks. The session oral presentations are available for download at http://www.mos-ak.org/sanfrancisco_2012/

The compact modeling panel discussion moderated by Larry Nagel concluded the MOS-AK/GSA workshop. Invited international academic researchers and modeling engineers reviewed the status of compact modeling standardization and agreed that the Verilog-A standard offers a unique platform for compact model developments, validation, exchange and implementation into commercial as well as open source CAD/EDA tools. The panelists also pointed out the needs of further Verilog-A standard extensions and broader Verilog-AMS language definitions to better support compact device modeling, in particular focusing on Analog/RF noise applications. It is also expected that open source developers will actively contribute to standards promotion, addressing the challenges of related CAD/EDA software developments, such as Verilog-AMS debuggers supporting new model validations; and full featured, integral Verilog-AMS simulators for semiconductor device model benchmarking.

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a spring Q2/2013 MOS-AK/GSA meeting in Munich (D), followed by a special compact modeling session at the MIXDES Conference in Gdynia (PL); and an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest (RO).

Extended MOS-AK/GSA Compact Modeling Committee

[read also recent press release]

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The 20nm Moore's Law Challenge - FinFET versus SOI technology... with John Chen, Nvidia

From Electronics weSRCH:

http://electronics.wesrch.com/weqEL1UYOB

Some say Moore's Law for semiconductors has stopped. But the world of 20nm technology is coming fast.  My guest, John Chen, Vice President, Wafer Foundry Group and Global Operations of Nvidia, was here to talk about it. He talks about the strengths and weaknesses of FinFET and SOI, including the power benefits and the design challenges.  Then we examine the question of Moore's Law slowing, followed up with the need for greater collaboration between fabless and foundry in a way that looks like a Virtual IDM.

The interview is in the original link, and it's quite interesting...

[mos-ak] [Final Program] 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee and the MOS-AK prime sponsors Agilent Technologies and Mentor Graphics, we have pleasure to invite to the 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012 http://www.mos-ak.org/sanfrancisco_2012/ The event will be organized in timeframe of the IEDM and CMC meetings.

Venue:

swissnex San Francisco

730 Montgomery Street

San Francisco, CA 94111, USA

Final Workshop Program <http://www.mos-ak.org/sanfrancisco_2012/>

Workshop Agenda:

• MOS-AK/GSA Workshop - Dec. 12, 2012 (9:00am - 5:00pm)
  
• 9:00am - 12:00 Morning Session
• 1:00pm - 4:00pm Afternoon Session
  
• 4:00pm - 5:00pm Panel: Status and Future of Verilog-A Compact Modeling Standardization
• Moderator: Larry Nagel
• 5:00pm End of the MOS-AK/GSA workshop

-- Extended MOS-AK/GSA Committee

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Workshop on Advanced Materials and Devices

The Workshop on Advanced Materials and Devices will be held on March 13 to 15, 2013, at the University of Havana, Cuba. This meeting is a continuation of the“Workshop Espana-Mexico-Brazil”, first organized on March 16 to 18 2011 at CINVESTAV, Mexico. As in its previous issue, the main objective of the Workshop is to discuss the results of research projects done by collaborating groups, as well as to plan future activities of interest to the participants.

The workshop will count with the participation of researchers from different universities of Spain, Mexico, Brazil and Cuba.

As a more general objective, the meeting is interested in including new colleagues from other places. R9 EDS Chapters committee is also interested in promoting Latin American EDS members to join to these activities.

The extended abstracts will be published and distributed at the Workshop.

Please link to the corresponding entry on this page, to download the format for preparing the abstract.

The deadline for abstract presentation is December 24, 2012.

Abstracts should be sent to mestrada@cinvestav.mx

Recommended hotels are Hotel Nacional and Hotel Habana Libre

Special prices for the activity will be posted son.

Other important information will be incorporated to the page as the activity approaches.

Organizing committee:

Rodrigo Picos Universitat del Illes Balears, Spain

Benjamin Iniguez Universitat Rovira I virgili, Spain

Magali Estrada CINVESTAV-IPN, Mexico

Maria Sanchez Universidad de la Habana

Visit semiconductorconnect.org

The semiconductorconnect.org aims to help the semiconductor industry connect - jobs with candidates, events with attendees, students with placements. [Read more...]

[mos-ak] [2nd announcement] 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012 http://www.mos-ak.org/sanfrancisco_2012/ The event will be organized in timeframe of the IEDM and CMC meetings.

Venue:

swissnex San Francisco

730 Montgomery Street

San Francisco, CA 94111, USA

Important Dates:

• Call for Papers - Oct. 2012
  
• on-line abstract submission: <http://www.mos-ak.org/sanfrancisco_2012/abstracts.php>
• Submission deadline - Nov. 15, 2012
  
• Final Workshop Program - Nov. 30 2012
  
• free on-line registration: <http://www.mos-ak.org/sanfrancisco_2012/registration.php>
• MOS-AK/GSA Workshop - Dec. 12, 2012
  

R&D Topics to be covered include the following:

• Advances in semiconductor technologies and processing
  
• Compact Modeling (CM) of the electron devices
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and IC Designs
  
• Foundry/Fabless Interface Strategies
  

-- Extended MOS-AK/GSA Committee

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[mos-ak] [Call for Papers] 10th International Workshop on Compact Modeling

10th International Workshop on Compact Modeling (IWCM 2013)

January 22 (Tuesday), 2013; Pacifico Yokohama, Yokohama, Japan

Scope:

The workshop provides an opportunity for the discussion and the presentation of advances in modeling and simulation of nano-scale devices and circuits.

Topics:

• Compact modeling for all kinds of devices
  
• Parameter extraction methodology and strategy
  
• Circuit simulation techniques and methods
  

Abstract Submission:

Authors are requested to prepare a camera-ready abstract with a minimum 2 and maximum 8 pages including figures for  publication in the workshop proceedings. The electronic file of the paper should be submitted in PDF or MS-Word format to hjm@hiroshima-u.ac.jp.  IWCM 2013 is held co-located with ASP-DAC 2013 and paper templates in LaTex and Word formats are downloadable from the ASP-DAC 2013 website. Deadline for abstract submission is November 30th, 2012.

Organization Committee:

Chair: H. J. Mattausch (Hiroshima University, Japan)

Co-Chair: M. Chan (Hong Kong University of Science & Technology, H.K.)

Committee Members: 

Y. Cao (Arizona State University, USA)

W. Grabinski (EPFL, Switzerland)

J. He (Peking University, China)

J. J. Liou (University of Central Florida, USA)

T. Nakagawa (AIST, Japan)

D. Navarro (Silvaco, Japan)

M. Miura-Mattausch (Hiroshima University, Japan)

Y. J. Park (Seoul National University, Korea)

Z. Yu (Tsinghua University, China)

Contact:

If you have any question, please contact hjm@hiroshima-u.ac.jp.

Registration is free, but Yen 2000 are requested for the proceedings.

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QucsStudio 1.4.2

A new version of QucsStudio has just been released for general use. The latest version is mainly  bug fixes but does contain a number of new/improved features. A list of the changes are given below:

• some corrections in help system
• component names in noise contribution analysis with subcircuit prefix
• reduced time step warnings in transient analysis
• bugfix: differential voltages in equations
• in equations: allow suffix in node names
• bugfix: directory MinGW\mingw32\bin\ exists again
• bugfix: crash in diagram dialog if clicking on empty variable area
• new component: photodiode
• new equation function: stoa()
• bugfix: spaces allowed between function name and "("
• added InP permittivity in property list
• bugfix: correct text in C++ symbol string
• error message for wrong index in equation variables

This is likely to be one of the last releases in the QucsStudio 1.4 series.  Work has started on QucsStudio series 2.0.0.  QucsStudio 2.0.0 is expected to offer users significant improvements in simulation and modelling capabilities.  The first of the new releases will coincide with the tenth anniversary of the first release of Qucs next year.

QucsStudio can be downloaded from the QucsStudio homepage at http://www.mydarc.de/DD6UM/QucsStudio/qucsstudio.html

Contact: Mike Brinson

[mos-ak] MOS-AK/GSA Bordeaux workshop press release

MOS-AK/GSA Modeling Working Group Holds Summer Workshop in Bordeaux

Experts Share Insight on Compact Device Modeling with Emphasis on Simulation-Aware Models
http://www.gsaglobal.org/2012/10/mos-akgsa-modeling-working-group-holds-summer-workshop-in-bordeaux/

SAN JOSE, Calif. (October 1, 2012) – The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, has delivered their 10th compact modeling workshop, presented on Sept. 21, 2012 as an integral part of the ESSDERC/ESSCIRC Conference in Bordeaux (F). The event was organized receiving full sponsorship provided by the leading industrial partners including Agilent Technologies (USA), LFoundry (D), CSEM (CH), STMicroelectronics (F), and AMS (A). The French Branch of IEEE EDS, FP7 COMON Project, Eurotraining and MOSIS Services were among the workshop technical program promoters. More than 50 international academic researchers and modeling engineers attended three sessions to hear 16 technical compact modeling talks and poster presentations. 

The workshop's three sessions focused on the nanowire TFET and organic TFT technologies, advanced compact modeling for analog/RF IC design application, computer-aided design (CAD), EDA simulations highlighting recent developments of Verilog-A compact models and its standardization. The 10th MOS-AK/GSA ESSDERC/ESSCIRC workshop was opened by invited researchers highlighting active women contributions to compact modeling R&D. The speakers discussed: the EKV model for LC-VCO optimization (M. H. Fino, UNL); physics-based analytical model of nanowire TFETs (E. Gnani, Uni. Bologna); analytical models for disordered and polycrystalline organic TFTs (M. Raja, Uni. Liverpool); Hall effect sensors performance assessment using 3D physical simulations (M.-A. Paun, EPFL); and physical compact model of a CBRAM cell (M. Reyboz, CEA/LETI).  

Afterward invited international modeling experts presented: device modeling DC measurements challenges (F. Sischka, Agilent Technologies); surface-potential-based compact model of AlGaN/GaN HEMT power transistors (P. Martin, CEA/LETI); millimeter-wave CMOS device modeling and issues (K. Okada, TITech); measurement and modeling of CMOS devices in short millimeter wave (M. Fujishima, Hiroshima University);  thermal network extraction in ultra-thin-body SOI MOSFETs (Y. S. Chauhan, UC Berkeley); compact modeling of SiC JFET power devices (M. Bucher, TUC Chania); SMASH-ACMI for integration and validation of Verilog-A compact models in a SPICE simulator (G. Depeyrot, Dolphin Integration); parametric yield-oriented IC design based on cumulative distribution function and open-source EDA tools (D. Tomaszewski, ITE); analytical calculation of surface-potential in AlGaAs/GaAs and AlGaN/GaN HEMT devices (S. Khandelwal analytical 2D model for source/drain band-to-band tunneling in silicon double-gate TFETs (M. Graef, THM) gate-level modeling for CMOS circuit simulation with ultimate FinFETs (N. Chevillon, InESS). The session oral and poster presentations are available for download at http://mos-ak.org/bordeaux/

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a winter Q4/2012 MOS-AK/GSA meeting in San Francisco, CA, USA, followed by a spring Q2/2013 MOS-AK/GSA meeting in Munich, a special compact modeling session at the MIXDES Conference in Gdynia, Poland (https://www.mixdes.org); and an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest, Romania.

About MOS-AK/GSA Modeling Working Group:

In January 2009, GSA merged its efforts with MOS-AK, a well-known industry compact modeling volunteer group primarily focused in Europe, to re-activate its Modeling Working Group. Its purpose, initiatives and deliverables coincide with MOS-AK's purpose, initiatives and deliverables. The Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact model standardization and related tools for model development, validation/implementation and distribution.www.gsaglobal.org/working-groups/analog-mixed-signal 

About GSA:

The Global Semiconductor Alliance mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective ecosystem through collaboration, integration and innovation. It addresses the challenges within the supply chain including IP, EDA/design, wafer manufacturing, test and packaging to enable industry-wide solutions. Providing a platform for meaningful global collaboration, the Alliance identifies and articulates market opportunities, encourages and supports entrepreneurship, and provides members with comprehensive and unique market intelligence. Members include companies throughout the supply chain representing 30 countries across the globe.www.gsaglobal.org

Bookmark the permalink.

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[mos-ak] C4P: 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012 http://www.mos-ak.org/sanfrancisco_2012/ The event will be organized in timeframe of the IEDM and CMC meetings.

Venue:

swissnex San Francisco

730 Montgomery Street

San Francisco, CA 94111, USA

Important Dates:

• Call for Papers - Oct. 2012
  
• Submission deadline - Nov. 15, 2012
  
• Final Workshop Program - Nov. 30 2012
  
• MOS-AK/GSA Workshop - Dec. 12, 2012
  

R&D Topics to be covered include the following:

• Advances in semiconductor technologies and processing
  
• Compact Modeling (CM) of the electron devices
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and IC Designs
  
• Foundry/Fabless Interface Strategies
  

Extended MOS-AK/GSA Committee

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[mos-ak] MOS-AK/GSA Bordeaux workshop on-line publications

The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, has delivered 10th subsequent compact modeling workshop which was organized on Sept. 21, 2012 as an integral part of the ESSDERC/ESSCIRC Conference in Bordeaux (F). The event was organized receiving full organization sponsorship provided by the leading industrial partners including Agilent Technologies (USA), LFoundry (D), CSEM (CH), STMicroelectronics (F), and AMS (A). The French Branch of IEEE EDS, FP7 COMON Project, Eurotraining and MOSIS Services were among the workshop technical program promoters. More than 50 international academic researchers and modeling engineers attended three sessions to hear 16 technical compact modeling talks and poster presentations.

The workshop's three sessions focused on the nanowire TFET and organic TFT technologies, advanced compact modeling for analog/RF IC design application, computer-aided design (CAD), EDA simulations highlighting recent developments of Verilog-A compact models and its standardization. The 10th MOS-AK/GSA ESSDERC/ESSCIRC workshop was opened by fifth invited female researchers highlighting active women contribution to compact modeling R&D. Afterward invited international modeling experts presented their recent modeling work. The session oral and poster presentations are available for download at http://mos-ak.org/bordeaux/

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: 

• winter Q4/2012 MOS-AK/GSA meeting in San Francisco, CA (USA) <http://www.mos-ak.org/sanfrancisco_2012/>
  
• spring Q2/2013 MOS-AK/GSA meeting in Munich (D)
  
• special compact modeling session at the MIXDES Conference in Gdynia, (PL) <https://www.mixdes.org>  
  
• autumn Q3/2013 MOS-AK/GSA workshop in Bucharest, (RO)
  

Extended MOS-AK/GSA Committee

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Posted by Adele HARS on August 31, 2012, at Advanced Substrate News

Power & Performance: GSS Sees SOI Advantages for FinFETS

Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage, Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI.
To those of us not deeply involved in the research world, much of this may seem to come out of nowhere.  But there’s a lot of history here, and in this blog we’ll take a look at what it’s all about, and connect a few dots.

The GSS IEDM ’11 Paper

GSS is a recent spin-off of Scotland’s University of Glasgow – but there’s nothing new to the research community about these folks.  The core GSS-U.Glasgow team has been presenting important papers on device modeling at IEDM (which is one of the most prestigious of our industry’s conferences) and elsewhere for many years.
At the risk of stating the obvious, accurate simulations are incredibly important. Technologists need to be able to predict what results they can expect from different possible transistor design options before selecting the most promising ones.  Then they also need to provide reliable models to designers who will use them before committing chips to silicon.  One of the biggest challenges is predicting variability, which as we all know is getting worse as transistors scale to ever-smaller dimensions.
At IEDM ’11 last December, GSS-U.Glasgow presented Statistical variability and reliability in nanoscale FinFETs.  This covered  “A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping…”.  Essentially they concluded that scaling FinFETs on SOI should be no problem – and in fact the statistical variability of a 10nm FinFET on SOI would be about the same as the industry’s currently seeing in 45nm bulk CMOS.
That paper was based on work that the GSS-U.Glasgow team had done on two major European projects: the EU ENIAC MODERN project, and the EU FP7 TRAMS project.  It’s perhaps worth looking a little more closely at what those projects are about – and who’s involved:

• A key objective of the MODERN (for Modeling and Design of Reliable, process variation-aware Nanoelectronic devices, circuits and systems) is to develop “effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance”.  Other partners in the project include ST, Leti, NXP, Infineon, Numonyx (now Micron) and Synopsys.
• The objective of the TRAMS (for ‘Tera-scale Reliable Adaptive Memory Systems’) project is “to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort”. Other partners in the project include Intel, imec, and UPC/BarcelonaTech.

READ MORE AT THE SOURCE

CMRF Workshop (at BCTM)

CMRF Workshop (at BCTM)
Wednesday October 3, 2012, in Portland, Oregon, USA

Session Chair: Colin McAndrew

As with previous years the Workshop on Compact Modeling for RF/Microwave Applications (CMRF) is being held in conjunction with BCTM. The workshop has an interactive dynamic, and this year includes a Forum of experts who will assess the present major needs in modeling.

1:00–1:30 PM – Advanced SiGe HBT Modeling with HICUM Level 0 (v1.3) for RF and mmW Applications
D. Celi and N. Derrier

This presentation deals with advanced bipolar modeling using the latest revision of HICUM/L0 (1.3). Following an overview of test structures and measurement setup used for bipolar transistors, the new HICUM/L0 formulations are described. Subsequently a workflow for parameter extraction is detailed that is suitable for advanced SiGe heterojunction bipolar transistors for mmW applications. As a last point the possibilities and limitations of the model and the parameter extraction are discussed.

1:30–2:00 PM – Dynamic Ageing Modeling for Reliability Simulation
B. Ardouin

Semiconductor device behavior is not static but changes over time, and the amount of change depends on details of the voltages and currents a device experiences. This presentation will review recent development of a dynamic ageing model for HiCuM 2.3 and provides details of Verilog-A implementation and pragmatic modeling issues related to self-consistent integration of transistor degradation in accelerated time based on realistic transient circuit operation.

2:00–2:30 PM – End-to-End Modeling for Handset Power Amplifiers – It’s Not Just Two Transistors!
P. Zampardi, Y. Yang, K. Kwok, B. Li, A. Metzger, C. Cismaru, H. Shao, W. Sun, and M. Fredriksson

The short design cycle for handset power amplifiers relies on accurate models for ALL components used in the design, not just the “two HBTs” used for the power transistors. As the complexity of these amplifiers (usually used in front-end modules) has increased, so has the required accuracy for simulating the package, control circuitry, and the RF chain itself. This presentation will show some of the challenges and solutions developed to address the development of high-yield commercial power amplifiers and the design flow for their realization.

2:50–3:20 PM – Practical Modeling: When Less is More
A. DiVergilio

The primary goal of compact modeling is to allow designs to be carried out quickly and efficiently. Therefore, model accuracy is not the only metric of model effectiveness. No matter what the circuit, significant portions of the design cycle can benefit more from rapid iteration than from absolute accuracy. Overly-complicated models slow down simulation and, at worst, prevent convergence all-together, especially for large designs. This presentation discusses trade-offs that can be made between speed and accuracy, emphasizing the flexibility that can be achieved through high-level modeling languages, such as Verilog-A, when applied to device-level model development.

3:20–4:20 PM – Forum: “Grand Challenges in Modeling”
Queen Marie Ballroom

Models are by definition imperfect, but what are the biggest opportunities for improvement that will have the biggest bang-for-the-buck in design? This forum will attempt to answer that question, and formulate a prioritized list of items that will be published on the BCTM web site.

Participants:

• Bertrand Ardouin (XMOD technologies)
• Adam DiVergilio (Tektronix)
• Mikhail Shirokov (Triquint Semiconductor)
• Peter Zampardi (Skyworks Solutions)
• Colin McAndrew (Moderator; Freescale)

CTFT 2012

4th International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation

This workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in joint collaboration with Cambridge University. A partial list of the areas of interest includes:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

The workshop organizers:
Department of Engineering, University of Cambridge, Cambridge, UK
Technical School of Engineering, University Rovira i Virgili, Tarragona, Spain

[mos-ak] Final Program: 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the technical program sponsor, as well as with the industrial sponsors Agilent Technologies, LFoundry, CSEM, STM, AMS we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

The final workshop program is available on-line: <http://mos-ak.org/bordeaux/> 

To register please visit official ESSDERC/ESSCIRC registration website.

- with regards - WG (for the MOS-AK/GSA Committee) 

––––––––––––––––––––––––––––––––––---------------- 

MOS-AK/GSA Bordeaux (F) Sept.21, 2012 

MOS-AK/GSA San Francisco, CA Q4 2012 

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Why- and how- to integrate Verilog-A compact models in SPICE simulators

A nice paper from Maria-Anna Chalkiadaki, Cédric Valla, Frédéric Poullet, and Matthias Bucher:

Why- and how- to integrate Verilog-A compact models in SPICE simulators

This article presents a fast and accurate way to integrate and validate Verilog-A compact models in SPICE-like simulators. Modifications in the models' Verilog-A source code may be required prior to their conversion into low-level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog-A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models. Copyright © 2012 John Wiley & Sons, Ltd.

Birthday (61) of the JUNCTION transistor

From EDN:

Bell Labs and primarily William Shockley announced the invention of the junction transistor at a press conference in Murray Hill, NJ, the first week of July, 1951.
Sources vary as to when the formal announcement was actually made, July 4, 1951, or July 5, 1951.
At the time, Shockley was with Bell Labs’ solid state physics group, a unit to which he was a group head and a unit that saw much internal competition.
This new type of transistor overcame problems created by earlier point-contact transistors, developed by Bell Labs’ Joe Bardeen and Walter Brattain without Shockley but based in part on his previous work. It is said that when the patent process began for the point-contact transistor, Shockley made an effort to have his name only placed on the patent and made sure his fellow engineers knew of that effort.
Shockley has been described as having a “tremendous ego” by his co-workers. He was also known as having openly racist views.
Although Shockley is often known as “the inventor” of the transistor and despite his reported ego, he was often noted as correcting such misstatement and noting that he led the effort with others involved. Notes made during the development of the junction transistor can be viewed here.
Shockley left Bell Labs a few years after working on the junction transistor and eventually became a professor emeritus of electrical engineering at Stanford. He died on campus in 1989 at the age of 79.

For more moments in tech history, see this blog.

NANOTEC-Tutorial at ESSCIRC/ESSDERC in Bordeaux on 09/17/2012

The NANO-TEC project will held a half day tutorial at the ESSDERC/ESSCIRC Conference in Bordeaux on Monday, September 17, 2012. This Tutorial will be on the ECOSYSTEMS TECHNOLOGY and DESIGN for NANOELECTRONICS in Europe and will present the current outcome of the EU project NANOTEC [read more...]

[mos-ak] C4P: Special Issue of IEEE TED on Advanced Modeling of Power Devices and Their Applications

Call for Papers

For the Special Issue of

IEEE Transactions on Electron Devices 

On

Advanced Modeling of Power Devices and Their Applications

The special issue on "Advanced Modeling of Power Devices and Their Applications" is devoted to the research and development activities on power devices, the correlation of modeling approaches to the physics of power devices and in particular on emerging models of advanced power devices for power circuit applications. 

The importance of accurate circuit design with power devices is increasing according to the necessity of realizing efficient energy consumption. High-voltage MOSFETs are also utilized in all kinds of consumer electronics, and electric vehicles are controlled by IGBT circuit, where an urgent task is to achieve better energy control at about 1 kV bias condition. Accurate and even predictable models based on a close correlation to the important physical effects occurring in such power devices are therefore highly desired for precise circuit design. Presently many investigations are also undertaken intensively for new materials such as SiC and GaN replacing Silicon for extremely high voltage applications e.g. beyond 10 kV. A good understanding of the device operation under such extremely high bias conditions requires a lot physical analysis, and as a result leads to more effective utilization of these power devices. Together with the strong self-heating effect, the dynamically changing resistivity makes convergence in circuit simulation unstable. Techniques and physical analysis to overcome such problems are also urgently requested. 

Due to the wide range of covered bias conditions and the large variety of device structures applied, a lack of  communication occurs in the high-voltage community even though the basic tasks are the same. Therefore, the objective of this special issue is to bring together a diversity of R&D activities and advancements in the physical analysis and modeling of MOS-based power devices and other types of emerging power devices including Bipolar, Thyristor and Diode. Models for active and passive components integrated in advanced silicon as well as new material technologies, statistical modeling and mixed-mode simulation are also of special interest. 

The requirements for modeling high-voltage devices on the part of the circuit design community are now much more demanding due to urgent necessity to reduce energy consumption, where the high-voltage devices play an important role. Submissions should address advances in device characterization, physical models, as well as applications preferably but not limited to the following areas:

1. Compact modeling of power devices such as high-voltage MOSFETs, Bipolar, Thyristor and IGBT for 

circuit applications from a few volts up to beyond 10kV.

2. Modeling of passive elements such as Diode, Inductor, Resistor.

3. Investigations on new material such as SiC and GaN and their applications.

4. Circuit simulation for real applications of power devices together.

5. Investigation for computation efficiency for circuit simulation

Please submit manuscript by using the following:
http://mc.manuscriptcentral.com/ted

MAKE SURE TO MENTION THE SPECIAL ISSUE IN THE COVER LETTER

Paper Submission Deadline: July 15, 2012 

Scheduled Publication Date: February, 2013 

Guest Editors: 

Mitiko Miura-Mattausch, Hiroshima University, mmm@hiroshima-u.ac.jp  

Narain Arora, Silterra Malaysia, narain@silterra.com

Ehrenfried Seebacher,  Austriamicrosystems AG, ehrenfried.seebacher@austriamicrosystems.com

Samar K. Saha, SuVolta, Inc., samar@ieee.org

If you have any questions about submitting a manuscript, please contact:

Jo Ann Marsh (j.marsh@ieee.org)

IEEE EDS Publications Office

445 Hoes Lane Piscataway NJ 08854

Phone: +1 732 562 6855   Fax: +1 732 562 6831

http://www.ieee.org/

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5th "Micro&Nano2012" Kokkini Hani, Heraklion, 7-10 October 2012

Fifth International Conference "Micro&Nano2012"
on Micro - Nanoelectronics, Nanotechnologies and MEMs
Aquis Arina Sand Hotel, Kokkini Hani, Heraklion
7-10 October 2012

This is the first Micro&Nano conference, which will be organized at Heraklion, Grete, by members of the Micro&Nano society affiliated with the Foundation for Research and Technology (FORTH) and University of Crete. The conference will be co-chaired by Dr. Georgios Konstantinidis and Prof. Alexandros Georgakilas.

The Conference combines an extensive scientific programme including oral and poster sessions with exhibition and social events.

The Conference aims at gathering together in an interactive forum all scientists and engineers working in the challenging areas of micro/nano-electronic and optoelectronic/photonic devices, MEMs and circuits, as well as the enabling nanotechnologies of material growth, synthesis and processing. It aims to stimulate discussions on the last achievements and new developments in this rapidly evolving field.

One of the key objectives of the Conference is to promote collaboration and partnership between different academia, research and industry players. A one day workshop, presenting indicative cases and reviewing experiences and perspectives in these domains in Greece and elsewhere, will follow the conference [read more...]

The Scariest Graph

Posted from SemiWiki:

The Scariest Graph I've Seen Recently

by

Paul McLellan

Published on 06-18-2012 02:34 PM

10 Comments

Everyone knows Moore's Law: the number of transistors on a chip doubles every couple of years. We can take the process roadmap for Intel, TSMC or GF and pretty much see what the densities we will get will be when 20/22nm, 14nm and 10nm arrive. Yes the numbers are on track.

But I have always pointed out that this is not what drives the semiconductor industry. It is much better to look at Moore's Law the other way around, namely that the cost of any given functionality implemented in semiconductors halves every couple of years. It is this which has meant that you can buy (or even your kid can buy) a 3D graphics console that contains graphics way beyond what would have cost you millions of dollars 20 years ago in a state of the art flight simulator.

But look at this graph:

This shows the cost for a given piece of functionality (namely a million gates) in the current process generation and looking out to 20nm and 14nm. It is flat (actually perhaps getting worse). This might not matter too much for Intel's server business since those have such high margins that they can probably live with a price that doesn't come down as much as it has done historically. And they can make real money by putting more and more onto a chip. But it is terrible for businesses like mobile computing that don't live on the bleeding edge of the maximum number of transistors on a chip. If you are not filling up your 28nm die and a 20nm die costs just the same (and is much harder to design) why bother? Just design a bigger 28nm die (there may be some power savings but even that is dubious since leakage is typically an increasing challenge).

If this graph remains the case, then Moore's Law carries on in the technical sense that you can put twice as many transistors on your chip if you can think of something clever to do with them and can find a way to keep enough of them powered on. But it means there is no longer an economic driver to move to a new process unless you have run out of space on the old one.

Since EDA mostly makes money on designs in new processes (because they need new tools which can be sold at a premium) this is bad for EDA. It actually doesn't make money on the first few designs coming through a new process because there is so much corresponding engineering to be done. But if the mainstream never moves, the cash-cow aspect of selling EDA tools to the mainstream won't happen. And just like there is no business selling "microprocessor design tools" since there are too few groups who would buy them and their needs are too different, there might never be a big enough market for "14nm design tools" to justify the investment.

So that's why this is the scariest graph in EDA.

[mos-ak] [2nd announcement] 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

[2nd announcement] 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012
http://mos-ak.org/bordeaux/

Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the the technical program sponsor, we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

Free on-line registration (open on June 18) 

http://www.mos-ak.org/bordeaux/registration.php

The terms of participation, intending participants and authors should also note the following dates: 

• Preannouncement - April 2012
• Call for Papers - May 2012
• Abstract submission deadline - July 2012
• On-line abstract submission (open on June 18):
• http://mos-ak.org/bordeaux/abstracts.php
• Final Workshop Program - Aug. 2012
• MOS-AK/GSA Workshop - Sept. 21, 2012 http://www.mos-ak.org/bordeaux/
• Morning Session
• Panel Discussion: "Status and Next Decade of European Compact Modeling"
• Poster Session 
• Afternoon Session

Speakers (tentative list): 

Prof. Maria Helena Fino, Universidade Nova Lisboa, P

Prof. Lidia Lukasiak, TU Warsaw, PL

Prof. Androula Nassiopoulou, IMEL Demokritos, GR

Prof. Elena Gnani, University of Bologna, I

Munira Raja. Uni. Liverpool, UK

Maria-Alexandra Paun, EPFL, CH

Sadayuki Yoshitomi, Toshiba, JP

Yogesh S. Chauhan, UC Berkeley, USA

Patrick Martin, Minatec, F

Daniel Tomaszewski, ITE Warsaw, PL

Further details and updates: <http://mos-ak.org/bordeaux/> 

Email contact: <workshops@mos-ak.org> 

- with regards - WG (for the MOS-AK/GSA Committee) 

––––––––––––––––––––––––––––––––––---------------- 

COMON Tranining Course Tarragona (SP) June 28-29, 2012

MOS-AK/GSA Bordeaux (F) Sept.21, 2012 

MOS-AK/GSA San Francisco, CA Q4 2012 

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Special IETE issue on Compact Modeling

Special IETE issue (May-June 2012 Volume 58; Issue 3 Page Nos. 179-242) on Compact Modeling: "Compact Modeling as a Bridge between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits" is available on-line with following articles:

1. A Hybrid Verilog-A and Equation-defined Subcircuit Approach to MOS Switched Current Analog Cell Simulation p. 181
   Mike E Brinson, Stefan Jahn, H Nabijou
2. Aging Model for a 40 V Nch MOS, Based on an Innovative Approach p. 191
   Filippo Alagi, Roberto Stella, Emanuele Viganó
3. Complex 2D Electric Field Solution in Undoped Double-gate MOSFETs p. 197
   Mike Schwarz, Thomas Holtij, Alexander Kloes, Benjamín Iñíguez
4. 2D Analytical Calculation of the Parasitic Source/Drain Resistances in DG-MOSFETs Using the Conformal Mapping Technique p. 205
   Thomas Holtij, Mike Schwarz, Alexander Kloes, Benjamín Iñíguez
5. RF Compact Modeling of High-voltage MOSFETs p. 214
   Antonios Bazigos, François Krummenacher, Jean-Michel Sallese, Matthias Bucher, Ehrenfried Seebacher, Werner Posch, Kund Molnár, Mingchun Tang
6. HSPICE Model of the Physical Resistor p. 222
   Petr Beták, Petr Zavrel
7. Enhanced Non-quasi-static Lauritzen Diode Model p. 226
   Lenka Sochová, Petr Beták, Ján Plojhár
8. Self-heating Parameter Extraction of Power Metal-oxide-silicon Field Effect Transistor Based on Transient Drain Current Measurement p. 230
   Risho Koh, Takahiro Iizuka
9. Extraction of Scalable Electrical Model for HV (600/800 V) MOS Transistors p. 237
   Lorenzo Labate, Simona Angela Cozzi, Roberto Stella

450mm Impact Report Now Available For Free Download

This unique and authoritative report identifies the activities required to attract investments and to support 450mm and other advanced research, innovation, prototyping and semiconductor production. This report was based on a 14-month study Future Horizons undertook, together with the French market research firm Decision, between January 2011 and February 2012.

A copy of the report can be downloaded from the Commission's website at: http://cordis.europa.eu/fp7/ict/nanoelectronics/documents/450mm-final-report.pdf

If you have any questions on the report on some of the wider 450mm issues, please do so via our website at www.futurehorizons.com or call +44 1732 740440.

[mos-ak] 2nd Training Course on Compact Modeling: Registration Open

The MOS-AK Group as main dissemination partner of the European COMON Compact Modeling Network is announcing series of the modeling events:

• 2nd Training Course on Compact Modeling (June 28-29)
  
• http://www.compactmodelling.eu/tccm2_programme.php
• 8th ICOE International Conference on Organic Electronics (June 25-27)
  
• http://www.icoe2012.net/
• 10th Graduate Student Meeting (June 21-22)
  
• http://sauron.etse.urv.es/events/workshop/

Visit also the compact modeling calendar at www.mos-ak.org

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