IEDM'2011 Abstract Submission Site is Now Open (Deadline: June 24, 2011)

IEDM Abstract Submission Site is Now Open - Abstract Submission
Deadline:   June 24, 2011

2011 IEEE International Electron Devices Meeting
The Annual Technical Meeting of the Electron Devices Society will be held at the
Washington Hilton, Washington, DC USA  - December 5-7, 2011

To view the IEDM Call for Papers and instructions for submitting an abstract to
the conference, visit:      http://www.ieee-iedm.org

IEEE International Electron Devices Meeting (IEDM) is the world’s pre-eminent
forum for reporting technological breakthroughs in the areas of semiconductor
and electronic device technology, design, manufacturing, physics, and modeling. 
IEDM is the flagship conference for nanometer-scale CMOS transistor technology,
advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale
devices and phenomenology, optoelectronics, devices for power and energy
harvesting, high-speed devices, as well as process technology and device
modeling and simulation.  

Starting this year (2011) there is an increased emphasis on circuit and device
interaction.  With ever increasing transistor count, nanometer design rules and
layout restrictions, circuit-device interaction is becoming critical to
providing viable technology solutions. This new emphasis includes
technology/circuit co-optimization, power/performance/area analyses, design for
manufacturing and process control, as well as CMOS platform technology and
scaling.

INCREASED PARTICIPATION IN THE FOLLOWING AREAS IS SOUGHT: 
 * Circuit-device interaction 
 * Energy harvesting
 * Biomedical devices
 * Power devices

Information about IEDM can be found at: http://www.ieee-iedm.org 
Twitter: http://twitter.com/ieee_iedm 
Facebook: http://www.facebook.com/pages/IEDM/131119756449 

MEETING HIGHLIGHTS 
 * New subcommittees (Circuit-Device Interaction and Nano Device Technology)
 * New for 2011:  90 Minute Tutorial Sessions on Emerging Topics, Saturday
afternoon, December 3
 * Three plenary presentations by prominent experts 
 * Invited papers on all aspects of advanced devices and technologies.
 * An Emerging Technology session. 
 * Two evening Panel discussions.
 * Presentation of IEEE/EDS awards. 
 * IEDM Luncheon presentation will be held on Tuesday, December 6.
 * Two short courses will be held on Sunday, December 4.

Further Information - All questions or inquiries for further information
regarding this meeting should be directed to the Conference Office at:

19803 Laurel Valley Place
Montgomery Village, MD 20886 USA
Tel: 301-527-0900, ext. 2
Email: iedm@his.com 
Local European Contact 

Stefan De Gendt, IMEC, Belgium
Local Asian Contact 
Norikatsu Takaura, LEAP, Japan
2011 Conference Chair 
Kazunari Ishimaru, Toshiba, Japan
Technical Program Chair 
Veena Misra, North Carolina State University, USA

If you know of any colleagues who may have a paper to contribute and have not
received this notice, please bring it to their attention.

Course on Statistical CMOS Variability and Reliability, San Jose CA, June 13th and 14th

Professor Asen Asenov, CEO of Gold Standard Simulations, will be delivering a comprehensive course (see the flyer) on variability and reliability issues and their impact on modern CMOS devices and design.

The course topics include, Variability classification,Sources of statistical variability, Simulation of statistical variability, Variability trends in conventional and novel MOSFETs, Random telegraph noise statistics, Statistical aspects of reliability, Statistical compact model strategies and Statistical circuit simulation. At this event there will also be a special lecture on Variability in FinFET devices.

For more information please visit: http://www.goldstandardsimulations.com/courses/ or get in touch with them at courses(at)goldstandardsimulations.com.

Papers in Solid-State Electronics Volume 62, Issue 1, (August 2011)

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates   Original Research Article

Pages 31-39
Darsen D. Lu, Mohan V. Dunga, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu

Research highlights

► A computationally efficient approximation for surface potential in FDSOI MOSFETs is developed. ► I–V and C–V models for FDSOI MOSFETs are derived without making the charge sheet approximation. ► The core model and non-ideal effect expressions are implemented in Verilog-A language. ► The model is symmetric with respect to V_ds = 0 and continuous in all regions of operation.


 An effective thermal circuit model for electro-thermal simulation of SOI analog circuits   Original Research Article

Pages 48-61
Ming-C. Cheng, Kun Zhang

Highlights

► A thermal circuit model is developed for SOI analog circuits. ► The model integrates a device thermal circuit with interconnect thermal networks. ► The device thermal circuit accounts for non-isothermal effects in SOI devices. ► Thermal networks for cross-coupled and parallel coupled wires are developed. ► The model is coupled with BSIMSOI for electro-thermal simulation of SOI circuits.



MOSFET modeling for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures: Case of an analog/digital 0.18 μm CMOS process   Original Research Article

Pages 115-122
P. Martin, A.S. Royet, F. Guellec, G. Ghibaudo

Research highlights

► Specific physical effects are observed in a cooled (77–200 K) 0.18 μm CMOS process. ► These effects are described and modeled for design of cryogenic IR CMOS imagers. ► Data on low frequency noise and transistor matching in MOSFET are also presented.



 Physics-based compact model for ultra-scaled FinFETs   Original Research Article

Pages 165-173
Ashkhen Yesayan, Fabien Prégaldiny, Nicolas Chevillon, Christophe Lallement, Jean-Michel Sallese

Highlights

► We propose a physical and explicit compact model for lightly doped FinFETs. ► This design-oriented model is valid for a large range of silicon Fin widths/lengths. ► It describes well the drain current, small signal parameters and capacitances. ► It takes into account all short-channel effects and quantum mechanical effects. ► This compact model needs a very few number of electrical parameters (4).



Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s   Original Research Article

Pages 174-184
Krishna Meel, R. Gopal, Deepak Bhatnagar

Highlights

► New 3-D front (back) gate threshold voltage models of FD-SOI MOSFETs are reported. ► Models solve 3-D Poisson’s equation using Green’s function as a tool. ► 3-D threshold voltage models include side wall, source/drain and back gate effects. ► Front and back gate charge coupling is incorporated in both the threshold voltages. ► Compact models of threshold voltages are amenable to circuit CAD tool.



Mobility analysis of surface roughness scattering in FinFET devices   Original Research Article

Pages 195-201
Jae Woo Lee, Doyoung Jang, Mireille Mouis, Gyu Tae Kim, Thomas Chiarella, Thomas Hoffmann, Gérard Ghibaudo

Highlights

► Mobility analysis of the surface roughness scattering along the different interfaces of FinFET devices. ► The sidewall and top surface drain current components were estimated from the total drain currents of different fin width conditions. ► The contribution of the surface roughness scattering was analysed and that on sidewalls was about three times stronger than on top surface for n-channel FinFETs.

[mos-ak] C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Helsinki on Sept.16 2011

C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Helsinki on Sept.16 2011
http://www.mos-ak.org/helsinki/

Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop in
Helsinki on Sept.16 2011 with special panel: 40th Anniversary of SPICE
(panelists tentative alphabetic list):
* Narain D. Arora, Siltera, USA
* Christian Enz, CSEM, CH
* Andrei Vladimirescu, EECS, Berkeley
* Andreas Wild, ENIAC - JU, EU
and MOS-AK/GSA Transistor Level IC Design Challenge Opening

The MOS-AK/GSA Workshop is HiTech forum to discuss the frontiers of
the electron devices modeling with emphasis on simulation-aware
models. Original papers presenting new developments and advances in
the compact/spice modeling and its Verilog-A standardization are
solicited. The main topics of the workshop are: (but are not limited
to):
* Compact Modeling (CM) of the electron devices
* VHDL-AMS/Verilog-A for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Transistor Level IC support
* Nanoscale CMOS devices and circuits
* Reliability and thermal management of electron devices
* Technology R&D, DFY, DFT and IC designs
* Foundry/Fabless interface strategies

The terms of participation:
Authors are asked to submit a short (~200words) abstract using on-line
submission form by JUNE 30 http://www.mos-ak.org/helsinki/abstracts.php

Intending authors should also note the following deadlines:
* Announcement and Call for Papers - May 2011
* on-line abstract submission deadline - June 30, 2011
* Final Workshop Program - August 2011
* MOS-AK/GSA Workshop - Sept. 16, 2011

On-line workshop registration: http://www.essderc2011.org/registration.php
Further details and updates: http://www.mos-ak.org/helsinki
Email contact: helsinki@mos-ak.org

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Papers for curious people... (may 25th 2011)

CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability

Stanzione, S.  Puntin, D.  Iannaccone, G. 
Page(s): 1456 - 1463
Digital Object Identifier : 10.1109/JSSC.2011.2120650

AbstractPlus | Full Text: PDF (1209KB)

This paper presents an extreme-low-power mixed-signal CMOS integrated circuit for product identification and anti-counterfeiting, which implements a physical unclonable function operating with a challenge-response scheme. We devise a series of circuits and algorithmic solutions based on the use of a process monitor and on the prediction of the erratic response bits which allow to suppress the effects of temperature, voltage supply and process variations in order to obtain a robust and reliable b... Read More »


 

A Supply-Rail-Coupled eTextiles Transceiver for Body-Area Networks

Mercier, P. P.  Chandrakasan, A. P. 
Page(s): 1284 - 1295
Digital Object Identifier : 10.1109/JSSC.2011.2120690

AbstractPlus | Full Text: PDF (1915KB)

This paper presents a transceiver that communicates over electronic textiles as an alternative, energy-efficient communication medium for body-area network (BAN) applications. The proposed eTextiles network architecture consists of a two-wire conductive yarn medium, body-worn nodes, and a basestation used for data collection and medium-access control. Fabricated in 0.18 $mu$m CMOS technology, the eTextiles transceiver employs supp... Read More »

Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness

Ye, Y.  Liu, F.  Chen, M.  Nassif, S.  Cao, Y. 
Page(s): 987 - 996
Digital Object Identifier : 10.1109/TVLSI.2010.2043694

Abstract | Full Text: PDF (1332KB)

The threshold voltage $({V}_{rm th})$ of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations which are too expensive in computation for statistical design. In this work, we develop an efficient SPICE simulation method and statistical variation model that accurately predict threshold variation as a function of dopant ... Read More »

On Functional Broadside Tests With Functional Propagation Conditions

Pomeranz, I.  Reddy, S. M. 
Page(s): 1094 - 1098
Digital Object Identifier : 10.1109/TVLSI.2010.2043695

AbstractPlus | Full Text: PDF (197KB)

Functional broadside tests were defined as broadside tests where the scan-in state is a reachable state. This ensures that during the functional capture cycles of the test, the circuit visits states that it can also visit during functional operation. As a result, it avoids overtesting that may occur with unreachable states. However, the scan-out operation at the end of a functional broadside test allows the observation of any fault effects that reached the state variables at the end of the secon... Read More »

 

Broadside and Functional Broadside Tests for Partial-Scan Circuits

Pomeranz, I.  Reddy, S. M. 
Page(s): 1104 - 1108
Digital Object Identifier : 10.1109/TVLSI.2010.2044049

AbstractPlus | Full Text: PDF (176KB)

Functional broadside tests were defined to address overtesting that may occur due to the detection of delay faults under nonfunctional operation conditions. Such conditions are made possible by scanning in unreachable states. Functional broadside tests were defined and studied in the context of full-scan circuits. In this work, we study the definition of broadside and functional broadside tests in partial-scan circuits. A unique property we show is that if the unscanned state variables are obser... Read More »

Papers in IEEE TED, vol 58, issue 6 (june 2011)

An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET

Jandhyala, S.  Mahapatra, S. 
Page(s): 1663 - 1671
Digital Object Identifier : 10.1109/TED.2011.2131654

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton–Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in ... Read More »

Statistical Model of Line-Edge and Line-Width Roughness for Device Variability Analysis

Hiraiwa, A.  Nishida, A.  Mogami, T. 
Page(s): 1672 - 1680
Digital Object Identifier : 10.1109/TED.2011.2131144

The authors propose a model of line-edge and line-width roughness (LER and LWR) of actual device patterns, which received some smoothing steps, for accurate estimation of device variability. The model assumes that LER/LWR has originally an exponential autocorrelation function (ACF) and is smoothed using another exponential function. The power spectrum of this ACF almost completely fits the experimental one of polycrystalline silicon lines, which were formed using plasma etching. The authors inve... Read More »

A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET

Bazigos, A.  Krummenacher, F.  Sallese, J.-M.  Bucher, M.  Seebacher, E.  Posch, W.  Moln??r, K.  Tang, M. 
Page(s): 1710 - 1721
Digital Object Identifier : 10.1109/TED.2011.2119487

This paper presents a novel physics-based analytical compact model for the drift region of a high-voltage metal–oxide–semiconductor field-effect transistor (HV-MOSFET). According to this model, the drift region is considered as a simple 1-D problem, just as that of a low-voltage inner MOS transistor. It exploits the charge-sheet approximation and performs linearization between the charge in the drift region and the surface potential. The drift region model combined with the standar... Read More »

Papers in IEEE EDL, vol 32, issue 6 (may 2011)

Modeling of Current-Return-Path Effect on Single-Ended Inductor in Millimeter-Wave Regime

Wang, H.  Zhang, L.  Yang, D.  Zeng, D.  Wang, Y.  Yu, Z. 
Page(s): 737 - 739
Digital Object Identifier : 10.1109/LED.2011.2136312

The effect of current return path (CRP) on the accurate modeling of single-ended inductors in the millimeter-wave regime has been investigated. A series of spiral inductors with different sizes, shapes, and CRP positions was fabricated in a 0.18-$muhbox{m}$ RF-CMOS process and measured up to 50 GHz. An analytical appended model for CRP is developed to characterize the effect, and its equivalent circuit is validated by measurement ... Read More »

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

Duarte, J. P.  Choi, S.-J.  Moon, D.-I.  Choi, Y.-K. 
Page(s): 704 - 706
Digital Object Identifier : 10.1109/LED.2011.2127441

A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk curre... Read More »

Modeling and Separate Extraction of Gate-Bias- and Channel-Length-Dependent Intrinsic and Extrinsic Source–Drain Resistances in MOSFETs

Bae, H.  Jang, J.  Shin, J. S.  Yun, D.  Lee, J.  Kim, T. W.  Kim, D. H.  Kim, D. M. 
Page(s): 722 - 724
Digital Object Identifier : 10.1109/LED.2011.2131116

A new technique for a separate extraction of the current-path-dependent resistance $(R_{{rm SD}0})$ from the contact-dependent source and drain resistances $(R_{rm Se} hbox{and} R_{rm De})$ is reported for a single MOSFET. We also report a technique for a separation of $V_{rm GS}$ -dependent source an... Read More »

Extraction of Separated Source and Drain Resistances in Amorphous Indium–Gallium–Zinc Oxide TFTs Through – Characterization

Bae, H.  Kim, S.  Bae, M.  Shin, J. S.  Kong, D.  Jung, H.  Jang, J.  Lee, J.  Kim, D. H.  Kim, D. M. 
Page(s): 761 - 763
Digital Object Identifier : 10.1109/LED.2011.2127438

Considering asymmetry caused by layout, process, and device degradation, separate extraction of the source and drain resistances, i.e., $R_{S}$ and $R_{D}$, respectively, from the total resistance $R_{rm TOT}$ is very important in the design, modeling, and characterization of amorphous indium–g... Read More »

Mechanism Analysis of Off-Leakage Current in an LDD Poly-Si TFT Using Activation Energy

Nakashima, A.  Kimura, M. 
Page(s): 764 - 766
Digital Object Identifier : 10.1109/LED.2011.2132112

We have analyzed the mechanism of off-leakage current in an lightly doped drain (LDD) poly-Si thin-film transistor by investigating the activation energy $E_{a}$. It is found that $E_{a}$ decreases as the gate and drain voltages increase. We have also discussed the mechanism using a device simulator. It is found that a hole channel is lightly formed in the LDD regio... Read More »

Evidence of a Novel Source of Random Telegraph Signal in CMOS Image Sensors

Goiffon, V.  Magnan, P.  Martin-Gonthier, P.  Virmontois, C.  Gaillardin, M. 
Page(s): 773 - 775
Digital Object Identifier : 10.1109/LED.2011.2125940

This letter reports a new source of dark current random telegraph signal in CMOS image sensors due to meta-stable Shockley–Read–Hall generation mechanism at oxide interfaces. The role of oxide defects is discriminated thanks to the use of ionizing radiations. A dedicated RTS detection technique and several test conditions (radiation dose, temperature, integration time, photodiode bias) reveal the particularities of this novel source of RTS. Read More »


 

Temperature Dependence of the Threshold Voltage Shift Induced by Carrier Injection in Integrated STI-Based LDMOS Transistors

Poli, S.  Reggiani, S.  Denison, M.  Gnani, E.  Gnudi, A.  Baccarani, G.  Pendharkar, S.  Wise, R. 
Page(s): 791 - 793
Digital Object Identifier : 10.1109/LED.2011.2135835

Large threshold voltage shifts $(Delta V_{t})$ are experimentally observed in n-channel lateral DMOS transistors under high current–voltage regime. The effect is enhanced by the gate voltage as well as by the ambient temperature $(T_{A})$ . By approximating the curves with the usually adopted power-law dependence ... Read More »

RF Model and Verification of Through-Silicon Vias in Fully Integrated SiGe Power Amplifier

Liao, H.-Y.  Chiou, H.-K. 
Page(s): 809 - 811
Digital Object Identifier : 10.1109/LED.2011.2136313

This letter proposes an RF model of through-silicon via (TSV) considering both skin-depth and lossy substrate effects up to 20 GHz. The TSV is fabricated in 0.18-$muhbox{m}$ SiGe BiCMOS process with the dimensions of 50 $muhbox{m}$ in diameter and 100 $muhbox{m}$ in depth. The equivalent circuit model... Read More »

Channel-Length-Dependent Transport Behaviors of Graphene Field-Effect Transistors

Han, S.-J.  Chen, Z.  Bol, A. A.  Sun, Y. 
Page(s): 812 - 814
Digital Object Identifier : 10.1109/LED.2011.2131113

This letter presents a detailed study of transport in graphene field-effect transistors (GFETs) with various channel lengths, from 5 $muhbox{m}$ down to 90 nm, using transferred graphene grown by chemical vapor deposition. An electron–hole asymmetry observed in short-channel devices suggests a strong impact from graphene/metal contacts. In addition, for the first time, we observe a shift of the gate voltage at the Dirac poi... Read More »

Marie Curie PhD position in Catania, Italy

Dear Colleague,

it is a pleasure to inform you that a Marie Curie Early Stage Researcher
position is available at the Institute for Microelectronics and
Microsystem of the National Research Council of Italy (IMM-CNR) in
Catania.
The position is on the topic "Physical issues at interfaces and
nanoscale in advanced SiC devices", and it is open in the framework of
the FP7 Marie Curie ITN - NetFISiC (Training NETwork on Functional
Interfaces for SiC).

You can find more information on the position in the following link:

http://ec.europa.eu/euraxess/index.cfm/jobs/jobDetails/33681023

Would you please inform all the potential applicants for this position
(graduated students in Physics, Engineering or Material Science ) about
this good opportunity.

Should you need more information, contact:

Fabrizio Roccaforte
CNR-IMM
Strada VIII n.5, Zona Industriale
I-95121 Catania
Italy
tel. +39-0955968226
fax. +39-0955968312
e-mail: fabrizio.roccaforte@imm.cnr.it

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, MAY 2011

A physically based, accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal-oxide-semiconductor field-effect transistors

1. M. A. Karim^1,2,*,
2. Q. D. M. Khosru¹

Article first published online: 12 MAY 2011

DOI: 10.1002/jnm.817

Copyright © 2011 John Wiley & Sons, Ltd.

Issue

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Early View (Online Version of Record published before inclusion in an issue)

Open Ph D scholarship in semiconductor device modeling

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be for four years. The monthly salary will be about 1000 Euro/month. The position will start in September 2011.

The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices, in particular nanoscale MOSFETs. It will be related to several European projects in which the hosting group participates, in particular the COmpact MOdelling Netwok (COMON), that is led by the hosting group (the so-called NEPHOS group) and the SQWIRE (Silicon Quantum WIREs) project, about junctionless nanowires.

The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.

Required documents for applicants


Applicants are required to send to the address specified below the following documents (in English or Spanish):

1) a full Curriculum Vitae (as complete as possible) with passport number

2) Copy of their diploma

3) copy of their passport

4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.

Candidates are requested to send their documents by e-mail to:

Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering

Universitat Rovira i Virgili (URV)

Avinguda Països Catalans, 26
43007 Tarragona (Spain)
Email: benjamin.iniguez@gmail.com
Tel: +34977558521 Fax:+34977559610

Deadline: May 31 2011

You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@gmail.com) for more information

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat and sauron.etse.urv.es

Spice simulation, Tina-TI, LTSpice, PSpice, and more

Spice simulation, Tina-TI, LTSpice, PSpice, and more: "I got a nice note from the irrepressible Mary Dunnie that Texas Instruments h..."

job offer at Mentor

As today (May 10, 2011), there is an open position as pre-sales engineer at Mentor. More details here.

π Raspberry Pi Foundation

The Raspberry Pi Foundation is a UK registered charity (Registration Number 1129409) which exists to promote the study of computer science and related topics, especially at school level, and to put the fun back into learning computing [read more...]

Reflections from ISSCC 2011

Sotiris Bantas, VP Technology, Helic Inc., has posted his reflections from ISSCC 2011. Surly you will enjoy reading this: http://goo.gl/HB0ka

TSMC not following Intel to Finfets at 22nm - waiting till 20nm

Nearly a decade ago, TSMC demo-ed a 25nm Finfet - what Intel calls a Tri-Gate - transistor [more at Mannerisms]

Celebrating engineering: EDN names 2010 Innovation Award winners

Celebrating engineering: EDN names 2010 Innovation Award winners: "San Jose, CA—In aceremony here Monday evening, EDN bestowed its 2..."

Category: EDA Tools and ASIC TechnologiesThe finalists in this category—Apache Design Solutions, GateRocket Inc, GlobalFoundries, and Mentor Graphic—are recognized for innovations in design automation tools that reduce cycle time, increase manufacturability, and improve the reliability of integrated circuits. "Tonight's winner has achieved two of the most difficult feats in the EDA industry," Technical Editor Mike Demler said. "First, it has a history of developing innovative, differentiated products. This latest innovation addresses the problem of simulating electro-static discharge that has challenged designers for many years. The second distinction is to leverage that success into a proposed IPO."

Winner: Apache Design Solutions

Intel And Seagate: Silicon Transistor And Magnetic Storage Density Maintain An Impressively Steady Improvement Rate - Brian's Brain | Blog on EDN

Intel And Seagate: Silicon Transistor And Magnetic Storage Density Maintain An Impressively Steady Improvement Rate - Brian's Brain Blog on EDN


Two fundamental technology breakthroughs in two days; these are the times that tech editors dream of! I’ve in the past drawn a correlation between Moore’s Law (named for Intel’s Gordon), a forecast of the pace of single-chip transistor integration increase over time first made in 1965, and the rate of capacity growth over time (said another way, cost-per-capacity) for both magnetic and semiconductor storage. Solid-state drives, of course, are direct beneficiaries of Moore’s prescience, but areal density increases in magnetic storage are at least as impressive if not more so.

[mos-ak] MOS-AK/GSA Paris Workshop Press Release

MOS-AK/GSA Modeling Working Group Holds Spring Workshop in Paris
Experts Share Insight on Compact Device Modeling with Emphasis on
Simulation-Aware Models

Press release: http://gsaglobal.org/news/article.asp?article=2011/0426

On-line publications: http://www.mos-ak.org/paris/

The MOS-AK/GSA Modeling Working Group has several upcoming events:
* special modeling session at the MIXDES Conference in Gliwice, Poland
(https://www.mixdes.org/Special_sessions.htm);
* autumn MOS-AK/GSA workshop in Helsinki, Finland;
* winter MOS-AK/GSA meeting in Washington, D.C., USA.

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TSMC lays out their 20nm roadmap, no disruption from Japan.

Cited from EDN: TSMC lays out their 20nm roadmap, no disruption from Japan.:

TSMC kicked off their annual Technology Symposium series in San Jose today. Founder, Chairman and CEO Morris Chang opened the proceedings by addressing concerns for how Japan’s disaster recovery will impact the foundry’s supply chain. Dr. Chang listed a number of issues that had been of concern; metal sputtering targets, CMP (chemical-mechanical polishing) slurry, raw silicon wafers, chemicals, tools and spare parts. However, he assured the audience, TSMC has been able to solve all supply problems and “everything is under control, no supply shortages will interrupt the production lines“.

TSMC does expect an impact on their customers, however, and their customer’s customers. Dr. Chang said that there will be some effect on the industry in Q2 and possibly into Q3, but the impact would be no more than two quarters. This will add to a slight softening in the world economy; including Chinese efforts to fight inflation, problems in Europe, some economic measures in U.S., with the end result being that 2011 will be less strong than TSMC had originally thought. The company is resetting their forecast from 7% growth down to 4%.

Dr. Chang then went on to describe how the semiconductor market drivers have changed; from PCs (1980-2000), to cell phones (2000 - 2010), to today’s “killer app” - mobile products, including smartphones, tablets, and any “devices you carry around“.

Moving to more technical topics, Dr. Chang predicted that the 20nm process that they have in development will provide 2X the performance over 28nm. TSMC has also begun investigation at 14nm, and “Moore’s law still has some distance to go“, according to Chang. He also noted that the company has “significant R&D” in 3D IC technology; including 2/2.5D interposers, TSV (through-silicon vias), and what the company refers to as “system-level scaling“.

Dr. Chang concluded by comparing TSMC’s capacity (2 - 12″ fabs produce up to 260,000 wafers/month), to competitors, stating that they are building capacity but they don’t have the technology, that what competitors have is not “effective capacity“. TSMC is also working on production of 450mm wafers. Pilot production is targeted for 2013-14, with an “intercept point” for production of 20nm in 2015-16.

The 20nm roadmap

Next up on the morning’s agenda was Dr. Shang-Yi Chiang, TSMC’s Sr. VP R&D, to go over TSMC’s advanced technology roadmap. Looking out to the next process node, Dr. Chiang said that the 20nm (20G) process will be available in Q3 2012. In the meantime, TSMC will offer4 versions at 28nm; LP, HPL, G, and HPM. HPM will combine high performance and low power, the sweet spot for ARM cores according to Dr. Chiang.

Dr. Chiang said that the migration to a new process node typically adds 2-3 process modules, but 5 new modules are needed for 20nm. The 20nm process node will be the last generation for planar transistors. The most expensive 20nm process module will be the change to double patterning. TSMC has developed software that will automatically apply DFM requirements to create the 2nd mask from design data.

TSMC’s 20G and 20SoC processes will offer >2X the performance and <0.75X the switching power compared to 28HP & 28HPM. A 20nm SRAM has been fabricated, but 100% yield has not been achieved yet. At 20nm, TSMC is seeing a sidewall interface effect that can dominate interconnect delays, now that line widths are approaching the mean-free path of electrons. According to Dr. Chiang, TSMC has developed a smoothing process that minimizes the effect of electrons literally bouncing off of the walls of interconnect.

TSMC says that they are innovating to extend immersion lithography to 20nm, but that NGL (next-generation lithography) will be required for nodes <20nm. Dr. Chiang said that TSMC plans to have an ASML EUV machine, the NXE-3100 at TSMC by mid-2011.

Nano-KISS: Advanced CMOS Devices

26-29 April 2011, Palgongsan-DAEGU, Korea

Nano-KISS is organized by Kyungpook National University (KNU) and Grenoble Insitute of Technology (NPG) via World-Class University and Brain Korea 21 projects. Pyeongsan academy, located in the famous Palgong provincial park, is a very attractive place for combining top level lectures with scientific interactions and recreational activities. The first edition in 2010 was dedicated to advanced SOI concepts and technologies. The School topics are changed every year.The program is divided in sub-topics such as to enable full-time participation or single-day participation.

Scientific Program nano-KISS 2011

Build accurate Spice models for low-noise, low-power precision amplifiers

Build accurate Spice models for low-noise, low-power precision amplifiers: "

System engineers require accurate models for all types of ICs, and they require Spice models to run comprehensive circuit simulations. Early Spice models had few nonlinear elements, minimizing simulation time at the cost of accuracy, but new methods let you increase the number of nonlinear elements and improve accuracy. You can create a multistage model for low-noise, low-power operational amplifiers. The model employs work from Analog Devices (Reference 1) and requires several architectural changes to model a low-noise, low-power precision amplifier. The model architecture processes the input signal through eight stages. You can easily calculate the parameters for the eight stages with a handheld calculator. To understand the model creation, you must have experience using Spice.

Although higher-speed amplifiers have multiple poles and zeros, this model is for a single-pole, 10-MHz amplifier. It lets you simulate the amplifier’s key ac and dc parameters. The model includes ac parameters for flicker and flatband noise, slew rate, CMRR (common-mode rejection ratio), gain, and phase. The model’s dc parameters are VOS (input offset voltage), IOS (input offset current), quiescent supply current, and output-voltage swing. The model uses the 25°C typical parameters (Reference 2). The closer you model the input stage to the actual amplifier, the more accurate your results will be. You can achieve an accurate ac representation of the amplifier’s performance using a few of the process parameters of the input-stage transistors or MOSFETs. This model’s architecture lets you model amplifiers with split supplies. There is no ground reference in any of the signal-processing blocks. After the differential-to-single-ended conversion, all internally generated node voltages are referenced to the midpoint of the power supplies, much like the actual operation of an amplifier."

Complete IC simulation requires a full toolbox of hardware and software

Complete IC simulation requires a full toolbox of hardware and software: "Discovering a design error after you send youraverage chip to manufacturing c..."

[mos-ak] Final Program MOS-AK/GSA Workshop in Paris

Please visit the MOS-AK/GSA Paris web site with the final workshop
program:
http://www.mos-ak.org/paris/

* Free On-line Registration Form:
http://www.mos-ak.org/paris/registration.php

* Venue:
Université Pierre et Marie Curie
LIP6 (UPMC)
4 Place Jussieu; Paris
Bâtiment ESCLANGON; Amphithéâtre ASTIER

* Agenda: 7-8 April 2011 MOS-AK/GSA Workshop
"Frontiers of the Compact Modeling for Advanced Analog/RF
Applications"

April 7 (13:00-16:00)
* half day/afternoon MOS-AK modeling session
* poster session introduction
* COMON Network meeting/session (members only)
* informal MOS-AK/COMON "modeling" dinner (individual selfpaid)

April 8 (9:00-16:00)
* morning MOS-AK Session
* poster session
* afternoon MOS-AK Session

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I've found this offer, which I'm sharing with you:

Looking for Modeling & Characterization Engineer. Please send resume to Goldie.Homan@onsemi.com or apply Job 10536 at http://www.onsemi.com/PowerSolutions/content.do?id=16367

Position Description As a Modeling Engineer in the Corporate R&D department, you will:

- Perform and analyze electrical measurements on various devices.
- Design test structures.
- Extract device SPICE models using ICCAP, UTMOST, MQA, and other in-house software packages.
- Support transfer methodology for models from TRD to Design Methodology.
- Document characterization and modeling work according to established procedures.
- Evaluate and support implementation of new characterization, modeling and methods.
- Provide performance assessment and feedbacks for device development engineering.
- Interface with Design Methodology, Design, Foundry and external customers to resolve characterization/modeling issues and improve characterization/modeling methods.
- Work jointly with modeling groups in CZ to perform characterization/modeling tasks.
- Perform other tasks as may be from time to time assigned.

Position Requirements Successful candidates for this position will have:

- A BS/MS/PhD in Electrical Engineering/Physics/Material Science/Chemical Engineering/Chemistry. MS/PhD preferred.
- In-depth understanding of semiconductor device physics and proficiency in DC, AC, and RF characterization.
- Previous Design/Device fabrication/Process integration experience desired.
- Ability to utilize statistical techniques is required.
- UNIX/LINIX shell, PERL programming experience is desired.
- Previous experience with BiPolar device design/simulation/modeling is a plus.
- Previous experience in RF parasitic extraction is a plus
- Demonstrated ability to work successfully with external groups is required.

Expiring in 11 days(March 25th, 2011)

ON Semiconductor: Search for Careers Worldwide onsemi.com

NASA To Host Open Source Summit

NASA will host a summit about open source software development on March 29-30 at the agency's Ames Research Center in Moffett Field, Calif. The event runs from 9 a.m. to 5 p.m. PDT on both days.

NASA's first Open Source Summit will bring together engineers, policy makers and members of the open source community. Participants will discuss the challenges within the existing open source policy framework and propose modifications to facilitate NASA's development, release and use of software. [more]

SPICE: a 40-year old open-source success story

From EDN:

SPICE: a 40-year old open-source success story
SPICE, the Simulation Program with Integrated Circuits Emphasis, has turned 40 years old. The IEEE has marked the occasion by designating the development of SPICE as a Milestone in Electrical Engineering and Computing. On February 23rd, the Computer History Museum hosted a celebration with a roundtable discussion by the individuals most responsible for bringing SPICE from its origin as a UC Berkeley student project to the huge commercial success it has achieved as the most widely used tool in the semiconductor industry.

The panel (from left to right) consisted of:

• Ron Rohrer - 2002 Kaufman Award recipient, who taught the class at UCB that developed the progenitor of SPICE, CANCER (Computer Analysis of Nonlinear Circuits, Excluding Radiation)
• Larry Nagel - as a student in Ron’s class, Larry took on CANCER as his Master’s degree project, and eventually developed the 1st successful implementation - SPICE2 - as his doctoral thesis.
• Kim Hailey - co-founder (with Shawn Hailey) of Meta-Software, where HSPICE was created.
• Ken Kundert - who led the development of Cadence’s Spectre simulator.
• David Hodges - Distinguished Professor Emeritus at UCB, the panel moderator, who is well known for leading the development of analog IC design in CMOS and for the original (Level-1) Shichman-Hodges MOS device model.

Read more.... in EDN

Analog/Mixed-Signal Behavioral Modeling

From Cadence... (see the original)

Analog/Mixed-Signal Behavioral Modeling – When to Use What

By Richard Goering on February 20, 2011

So when to use what? The conservative style provided by Verilog-A and Verilog-AMS is useful when there are significant accuracy requirements. This approach can potentially provide a 50-100X speedup over SPICE, but it all depends on how good your modeling is. "If you're a poor modeler, there's a chance you could end up with a model that's as slow as SPICE simulation or even slower," Walter warned.
Real  number modeling, also available through Verilog-AMS with the wreal data type, brings real number values into event-driven digital simulation. It thus has the speed benefits of digital simulation and can leverage the metric-driven verification methodology that's increasingly used by digital engineers. It's good when there are hard performance requirements and limited accuracy requirements. For example, wreal is very useful for full-chip mixed-signal simulations.
The following chart shows the accuracy/speed tradeoff ranges provided by various analog/mixed-signal modeling alternatives. Note that the conservative modeling style has a broad possible range, depending on how good the modeling is.
Also important is the modeling effort. Here we can see that conservative models require the most amount of effort. "You can potentially spend days, weeks, months to develop good behavioral models," Walter said. Wreal models are relatively fast to develop because they're less detailed. An important rule of thumb: "Model what you need, not what you can."

Microelectronics Journal, in-press, february 2011

Modeling of threshold voltage of a quadruple gate transistor

Md. Gaffar, Sayed Ashraf Mamuna, and Md. Abdul Matina

Available online 24 February 2011.
Abstract

In this paper, a three dimensional analytical solution of electrostatic potential is presented for undoped (or lightly doped) quadruple gate MOSFET by solving 3-D Poisson's equation. It is shown that the threshold voltage predicted by the analytical solution is in close agreement with TCAD 3-D numerical simulation results. Numerical simulation, self-consistent Schrodinger–Poisson equations, calibrated by 2D non equilibrium green function simulation, are used.

The First Full-Color Display with Quantum Dots

Rodrigo Picos (rpicosg@gmail.com*) has sent you an article from TechnologyReview.com! Click below to read the article: The First Full-Color Display with Quantum Dots Samsung's new four-inch display could eventually lead to flexible screens. By Prachi Patel If clicking on the title above does not work, paste the link below into your web browser: http://www.technologyreview.com/computing/32407/ *The sender's identity has not been verified. Click here to read Technology Review's Privacy Policy.

SPICE Circuit Simulator Named IEEE Milestone

Simulating a circuit with SPICE is the industry-wide standard way to verify operation at the transistor level before manufacturing an IC. The program has become so ubiquitous that engineers often say they are going to “SPICE a circuit” when they are about to test one. To mark the 40th anniversary of SPICE—the Simulation Program with Integrated Circuit Emphasis—IEEE has designated its creation an IEEE Milestone in Electrical Engineering and Computing.

SPICE was made publicly available in 1971 so that chip designers could modify it—an early example of open-source software. Two years later, SPICE became well known after it was described in a paper by Pederson at the 16th Midwest Symposium on Circuit Theory, in Waterloo, Ont., Canada. During the next few years, developers around the world began using and modifying SPICE, leading it to become the industry standard it is today. “What happened was truly phenomenal,” Nagel wrote in “The Origins of SPICE.” “Within a few years, SPICE had achieved acceptance at almost all electrical engineering schools [for use in teaching] and had [spawned] a cottage industry to supply SPICE derivatives to the rapidly expanding integrated circuit industry.”

[Read more by Anna Bogdanowicz @ IEEE]

Papers in SSE (vol 57 , issue 1, March 2011)

Analytical threshold voltage model for lightly doped short-channel tri-gate MOSFETs

A. Tsormpatzoglou, D.H. Tassis, C.A. Dimitriadis, G. Ghibaudo, N. Collaert, G. Pananakakis


Generic complex-variable potential equation for the undoped asymmetric independent double-gate MOSFET

Adelmo Ortiz-Conde, Francisco J. García-Sánchez

Research highlights

► Single completely generic equation of channel potential for undoped asymmetric independently driven double-gate MOSFETs. ► Channel potential equation is based on complex variables and is valid for all values of front and back-gate bias. ► The unified nature of the proposed equation provides a better basis for global physical insight. ► Several examples, including the all important fully symmetric case, are analyzed.


 Compact modeling of CMOS transistors under variable uniaxial stress

Nicoleta Wacker, Harald Richter, Mahadi-Ul Hassan, Horst Rempp, Joachim N. Burghartz

Research highlights

► We propose a method to simulate the effect of uniaxial stress on MOSFETs. ► The method is valid for any drain current and stress directions in (001) Si plane. ► It can perform static and dynamic simulations, in linear and saturation regions. ► It is simulator-independent and does not depend on the source of uniaxial stress. ► It is adaptable to other bulk CMOS nodes and to other technologies such as SOI.


 A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

F. Lime, R. Ritzenthaler, M. Ricoma, F. Martinez, F. Pascal, E. Miranda, O. Faynot, B. Iñiguez

Research highlights

► Valid for long-channel undoped ADGMOSFETS with independent gate operation. ► Fully analytical and explicit derivation with no iterative solutions. ► Accessible front and back gate charges, potentials and currents. ► Unification of symmetric and asymmetric cases. ► Physical solutions similar to classical MOS theory.


In-depth physical investigation of GeOI pMOSFET by TCAD calibrated simulation

B. Grandchamp, M.-A. Jaud, P. Scheiblin, K. Romanjek, L. Hutin, C. Le Royer, M. Vinet

Research highlights

► We performed 2D simulations of germanium-on-insulator fully-depleted pMOSFET. ► Interface traps, mobility and leakage were calibrated versus experimental data. ► The prediction of electrical characteristics is accurate for several gate lengths. ► These simulations help in finding guidelines for improving the on-state current.


 Mobility in ultrathin SOI MOSFET and pseudo-MOSFET: Impact of the potential at both interfaces   

G. Hamaide, F. Allibert, F. Andrieu, K. Romanjek, S. Cristoloveanu

Research highlights

► Biasing the back interface in accumulation while extracting carrier mobility in FD-SOI MOSFETs leads to underestimated values. ► Apparent mobility degradation with decreasing film thickness in ultra-thin SOI MOSFET or Pseudo-MOSFET measurement is due to an additional component of the vertical electric field. ► In Pseudo-MOSFET measurements, the additional component of the vertical electric field comes from the traps and charges at the free-surface of the sample. ► We propose a new model to take this additional component of the vertical electric field into account.

Is SPICE good enough for tomorrow's analog?

by Nagel, L.W.; McAndrew, C.C.;
IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2010),
Digital Object Identifier: 10.1109/BIPOL.2010.5668096
Publication Year: 2010 , Page(s): 106 - 112

"The answer to the question posed in the title is an emphatic yes! Because SPICE is fairly general purpose and is not tied to any particular technology (not even only semiconductors), SPICE will play a significant role in the design of integrated circuits for a long time. SPICE will not be used to simulate billion transistor circuits, of course, but instead it will play a key role in developing the devices, device models, building blocks, and behavioral models for the building blocks for the billion transistor chips. SPICE will continue to play the role of the foundation of the integrated circuit design infrastructure." [Nagel, L.W.; McAndrew, C.C.]

[mos-ak] C4P MOS-AK/GSA Workshop at UPMC/LIP6 Paris on 7-8 April 2011

C4P MOS-AK/GSA Workshop at UPMC/LIP6 Paris on 7-8 April 2011
http://www.mos-ak.org/paris/

Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop at
UPMC/LIP6 Paris on 7-8 April 2011

The MOS-AK/GSA Workshop is HiTech forum to discuss the frontiers of
the electron devices modeling with emphasis on simulation-aware
models. Original papers presenting new developments and advances in
the compact/spice modeling and its Verilog-A standardization are
solicited. The main topics of the workshop are: (but are not limited
to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Reliability and thermal management of electron devices
* Technology R&D, DFY, DFT and IC designs
* Foundry/Fabless interface strategies

The terms of participation:
Authors are asked to submit a short (~200words) abstract using on-line
submission form by MARCH.1st:
http://www.mos-ak.org/paris/abstracts.php

Intending authors should also note the following deadlines:
* Call for Papers - Feb.2011
* Notification of preliminary acceptance - March 2011
* Final Workshop Program - end of March 2011
* MOS-AK/GSA Workshop - 7-8 April 2011

Further details and updates http://www.mos-ak.org/paris/
On-line workshop registration http://www.mos-ak.org/paris/registration.php

Local Organizing Committee:
Marie-Minerve Louerat, UPMC/LIP6
Ramy Iskander, UPMC/LIP6

Technical Program Committee:
Marie-Minerve Louerat, UPMC/LIP6
Andrei Vladimirescu, ISEP/UCB
Costin Anghel, ISEP
Ramy Iskander, UPMC/LIP6

Extended MOS-AK/GSA Committee:
Lisa Tafoya, Vice President, Global Semiconductor Alliance (GSA)
Chelsea Boone, GSA; Director of Research
Kayal Rajendran, GSA; Senior Research Analyst
Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster
Roberto Tinti, Agilent EEsof Division
MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil
Sergio Bampi, UFRGS, Brazil
Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Alexander Petr, XFab
Co-Chair: Prof. Benjamin Iniguez, URV
James Victory, Sentinel-IC
MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Xing Zhou, NTU, Singapore
A.B. Bhattacharyya, JIIT, India

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IEEE SCV EDS: February 8 Photovoltaic Technology Talk

Talk on photovoltaic technology on Feb. 8th. Module reliability is a key issue in photovoltaic technology.

Feb 8th:

Dr. Glenn Alers – UC Santa Cruz,

“Photovoltaic Module Reliability and Failure Analysis: Enduring a storm”

(Next month event) March 1st:

Dr. Geert Vandenberghe, IMEC,

“Lithography Options for 22nm and Beyond”

More information at the IEEE Santa Clara Valley EDS Chapter Home Page
http://www.ewh.ieee.org/r6/scv/eds/

Molybdenite touted as 'material to revolutionize electronics'

Molybdenite touted as 'material to revolutionize electronics': "A material called molybdenite is being touted by researchers as having distin..."

High school teacher creates microfluidic devices using a photocopier

Photo courtesy Harvard University [read more]

Postdoc position on compact device modeling in Spain

As Professor in the Universitat Rovira i Virgili (Tarragona, Spain), I am going to apply for a postdoctoral position (funded by the Spanish Ministry under the Programa Juan de la Cierva) related to the European projects we participate in: the SQWIRE project (a project about technology, characterization and modeling of Si nanowires) and the Compact Modeling Network, COMON (of which I am the coordinator).

The candidate should be a person who holds a PhD as awarded within the three years prior to the date when the period for presentation of application forms closes. The Ph D must have been obtained later than January 1 2007. If the candidate does not hold a PhD yet, the deadline to be awarded a PhD is the date of publication of the Awarding Resolution in the Ministry of Education and Science web site.

The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. In any case, it will be related to the European projects in which we participate. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by these European projects: nanowire FETs, multi-gate MOSFETs (FinFETs, DG MOSFETs,...), High Voltage MOSFETs and advanced HEMTs.

The postdoc position, which will be a contract, will have a duration of up to 3 years. The net salary will be around 1900 Euro/months.

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: February 8 2011

MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat

Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona
SPAIN.

About Tarragona:

Tarragona is located on the Mediterranean, in the heart of the Costa Daurada, in the south of Catalonia, about 100 Km south from Barcelona. Tarragona is well connected to Barcelona by highway, and frequent trains and buses. It has also a direct bus connection with Barcelona Airport. Besides, it has high-speed rail connection with Madrid and Barcelona.

Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. F On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public. Among the citizens of Tarragona, it has moreover fomented knowledge of, pride in and respect for the city.

Speaking about Tarraco’s climate, the famous Roman poet Virgil wrote: “The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring.” Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe. The city has a population of 120,202 inhabitants, and the native tongue is Catalan, but everybody speaks also Spanish, which is also official in Catalonia. Many people can also speak English (especially the young people) or French.

Papers in SSE (vol 56, issue 1, february 2011)

Temperature model for Ge₂Sb₂Te₅ phase change memory in electrical memory device   Original Research Article

Pages 13-17
Daolin Cai, Zhitang Song, Houpeng Chen, Xiaogang Chen

Research highlights

► Temperature model is constituted by an active region and a dispersed-heat region. ► Calculated and simulated the radius and crystalline fraction. ► Crystalline fraction and temperature increase with the reset voltage increasing.


 Microwave noise modeling of FinFETs   Original Research Article

Pages 18-22
Giovanni Crupi, Alina Caddemi, Dominique M.M.-P. Schreurs, Wojciech Wiatr, Abdelkarim Mercha


 Comprehensive numerical simulation of threshold-voltage transients in nitride memories   Original Research Article

Pages 23-30
Aurelio Mauri, Salvatore M. Amoroso, Christian Monzio Compagnoni, Alessandro Maconi, Alessandro S. Spinelli

Research highlights

► We present a complete model to describe charge trap devices behavior. ► In this study any mathematical aspect regarding holes and electrons is detailed modeled. ► Experimental data coming from different TANOS and SONOS devices are correctly reproduced.


 A unified short-channel compact model for cylindrical surrounding-gate MOSFET   Original Research Article

Pages 40-46
Bastien Cousin, Marina Reyboz, Olivier Rozeau, Marie-Anne Jaud, Thomas Ernst, Jalal Jomaah

Research highlights

► A compact model of short-channel effects for GAA MOSFET has been developed. ► The model uses a well-known extraction method making the model simple and accurate. ► Each term is used in a model core in order to provide a short-channel correction. ► The compact model is well described and is suitable with circuit design tools. ► The model is validated using TCAD simulations for all gate lengths down to 10nm.



Physical limitations of the diffusive approximation in semiconductor device modeling   Original Research Article

Pages 60-67
Tigran T. Mnatsakanov, Alexey G. Tandoev, Michael E. Levinshtein, Sergey N. Yurkov

Research highlights

► New criteria for occurrence of the diffusion mode were formulated. ► The applicability limits of the diffusion approximation in simulation were found. ► The analytical results are confirmed by a numerical experiment.


 Direct determination of threshold condition in DG-MOSFETs from the g_m/I_D curve   Original Research Article

Pages 89-94
Ana Isabela Araújo Cunha, Marcelo Antonio Pavanello, Renan Doria Trevisoli, Carlos Galup-Montoro, Marcio Cherem Schneider


Dynamic model of AlGaN/GaN HFET for high voltage switching   Original Research Article

Pages 135-140
Alexei Koudymov



A surface potential based drain current model for asymmetric double gate MOSFETs   Original Research Article

Pages 148-154
Pradipta Dutta, Binit Syamal, N. Mohankumar, C.K. Sarkar

Research highlights

► We model a surface potential based drain current for asymmetric DG MOSFETs. ► The model is applicable for both heavily and lightly doped Silicon channel. ► The surface potential at both the gates are solved using proper Iterative techniques. ► The effect of volume inversion is shown in case of lightly doped channel.



 AlGaN/GaN hybrid MOS-HEMT analytical mobility model   Original Research Article

Pages 201-206
A. Pérez-Tomás, A. Fontserè

Research highlights

► The hybrid normally-off switch AlGaN/GaN MOS-HEMT combines two main advantages: ► The MOS gate control and the high 2DEG mobility in AlGaN/GaN drift region. ► Here, we present simple analytical modeling of the on-resistance of a hybrid MOS-HEMT. ► We investigate the layout, the MOS channel mobility, the effect of a high-k and the temperature. ► The model can aid to understand the device physics and is compatible with TCAD simulation packages.



Mobility degradation and transistor asymmetry impact on field effect transistor access resistances extraction   

Pages 214-218
J.C. Tinoco, A.G. Martinez-Lopez, J.-P. Raskin

[uSG] New Website

Microelectronics Students' Group website is finished and can be visited at: http://usgroup.eu where you can also find out more about usgroup, as well as their projects and activities. You can also follow usgroup on Twitter and on Facebook. For further information please contact:

Daniel Oliveira (Microelectronics Students' Group)
Faculdade de Engenharia da Universidade do Porto
Rua Dr. Roberto Frias, s/n 4200-465 Porto PORTUGAL

mail: cmos@fe.up.pt, web: cmos.fe.up.pt