1952: British radar engineer Geoffrey Dummer introduces the concept of the integrated circuit at a tech conference in the United States. The world is about to change. Read more... by www.wired.com
May 8, 2010
May 7, 1952: The Integrated Circuit …
1952: British radar engineer Geoffrey Dummer introduces the concept of the integrated circuit at a tech conference in the United States. The world is about to change. Read more... by www.wired.com
Organic Transistor Could Outshine OLEDs
”The light-emitting transistor is a remarkably versatile device architecture,” says Alan Heeger, a physics professor at the University of California, Santa Barbara. Heeger’s lab developed an OLET inverter circuit earlier, but its quantum efficiency was much lower. He called the 5 percent external quantum efficiency ”remarkable,” because it suggests that nearly 100 percent of the carriers in the emissive layer are emitting photons. ”If that is indeed true,” Heeger says, ”they have made an important step forward.”
May 7, 2010
3rd International Workshop on Copact TFT Modeling for Circuit Simulation: Deadline Extended
The 3rd International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation (C-TFT) will be held in Tarragona on July 2 2010.
Deadline for abstract submission has been extended:
- Deadline for abstract submission: May 19, 2010
- Notification of acceptance: May 26, 2010
- Camera-ready version: Jun 18, 2010
The C-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London.
Topics:
A partial list of the areas of interest includes:
- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat
This event will be held in coordination with the Training Courses on Compact Modeling (June 30-July 1) and the Graduate Student Meeting on Electronic Engineering (June 28-29).
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
Deadline for abstract submission has been extended:
- Deadline for abstract submission: May 19, 2010
- Notification of acceptance: May 26, 2010
- Camera-ready version: Jun 18, 2010
The C-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London.
Topics:
A partial list of the areas of interest includes:
- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat
This event will be held in coordination with the Training Courses on Compact Modeling (June 30-July 1) and the Graduate Student Meeting on Electronic Engineering (June 28-29).
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
May 5, 2010
EPFL MicroNano Fabrication Annual Review Meeting
The Networking Event organized by the EPFL Center of MicroNanoTechnology (CMi)
Date: Tuesday May 18th, 2010
Time: 09h30 - 17h00
Place: EPFL Lausanne, Salle Polyvalente, Centre Est, CE 1 515
Program :
The presented topics include:
Date: Tuesday May 18th, 2010
Time: 09h30 - 17h00
Place: EPFL Lausanne, Salle Polyvalente, Centre Est, CE 1 515
Program :
The presented topics include:
- Biomedical Applications (Microfluidics, Cellular-Manipulation, Microelectrode Arrays, Molecules Detection, BioMicroNanoSystems, ...)
- Optics (Nanophotonics, Optomechanics, Optofluidics, MOEMS, ...)
- Micro and Nanoelectronics (Nanowires, High-Q Resonators, RF MEMS and Switches, 3D integration, CMOS, ...)
- Nanostructure Physics (III/V Devices, Nanotubes, Nanowires, Nanomechanics, ...)
- Material Sciences (Graphene, Polymers, Piezoelectric Ceramics, Photovoltaic Materials, Micro Fuel Cells, ...)
- MEMS, NEMS (Motors, Tweezers, Sensors and Actuators, Micro and Nanomechanics, ...)
- Micro and Nanofabrication Technologies (Self-Assembly, EBEAM Lithography, Dry Etching, Thin Films, Photolithography, FIB, CMP, ...)
- Packaging and Assembly
May 4, 2010
Compact Modeling: Principles, Techniques and Applications
Gildenblat, Gennady (Ed.)1st Edition., 2010, 545 p., Hardcover
ISBN: 978-90-481-8613-6
Erscheinungstermin: Juli 2010
May 3, 2010
[mos-ak] MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville: 1st announcement
MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville
*** 1st announcement ***
*** 1st announcement ***
Date: September 17, 2010
Venue: Barceló Hotel Renacimiento
Co-Located With:
* 40th European Solid-State Device Research Conference (ESSDERC):
http://www.essderc2010.org
* 36th European Solid-State Circuits Conference (ESSCIRC) :
http://www.esscirc2010.org
* CMC Meeting (Q3 Event in Madrid): http://www.geia.org/index.asp?bid=597
More MOS-AK/GSA information and updates: http://www.mos-ak.org/seville/
Extended MOS-AK/GSA Committee:
===========================
http://www.mos-ak.org/committee.html
===========================
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster
MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil
MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Sebastian Schmidt, XFab
Co-Chair: Prof. Benjamin Iniguez, URV
MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Xing Zhou, NTU, Singapore
===========================
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May 2, 2010
Thoughts on Directions for Silicon Technology Development as we Approach the End of CMOS Scaling
Speaker: Dr. Tak H. Ning, IBM and IEEE Fellow, and co-author of the Taur & Ning textbook now in its second edition.
Date: TUESDAY, May 11, 2010; Time: 6:00 PM - Pizza, 6:15 PM – Lecture; Cost: Free
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051
Web link: http://www.ewh.ieee.org/r6/scv/eds/
Contact: Sandeep Bahl
Date: TUESDAY, May 11, 2010; Time: 6:00 PM - Pizza, 6:15 PM – Lecture; Cost: Free
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051
Web link: http://www.ewh.ieee.org/r6/scv/eds/
Contact: Sandeep Bahl
Apr 29, 2010
POWER/HVMOS Devices Compact Modeling
POWER/HVMOS Devices Compact ModelingW. Grabinski and T. Gneiting, (Eds.)
1st Edition., 2010, V, 300 p., Hardcover
ISBN: 978-90-481-3045-0
TABLE OF CONTENTS
CHAPTER 1: Numerical Power/HV Device Simulations; Oliver Triebl and Tibor Grasser.
1st Edition., 2010, V, 300 p., Hardcover
ISBN: 978-90-481-3045-0
Content Level » Research
Keywords » HV EKV, HV HiSIM,MM20, compact modeling - LDMOS, VDMOS, quasi-saturation, self heating - power, high voltage semiconductor devices
Keywords » HV EKV, HV HiSIM,MM20, compact modeling - LDMOS, VDMOS, quasi-saturation, self heating - power, high voltage semiconductor devices
CHAPTER 1: Numerical Power/HV Device Simulations; Oliver Triebl and Tibor Grasser.
CHAPTER 2: HiSIM-HV: A scalable, surface-potential-based compact model for symmetric and asymmetric high-voltage MOSFETs; Hans J. Mattausch, Norio Sadachika, M. Yokomichi, M. Miyake, T. Kajiwara, H. Kikuchihara, U. Feldmann, and M. Miura-Mattausch.
CHAPTER 3: MM20 HVMOS Model: a surface-potential based LDMOS model for circuit simulation; Annemarie Aarts and Alireza Tajic.
CHAPTER 4: Practical HV DMOS modeling using HVEKV; Yogesh Singh Chauhan, Francois Krummenacher and Adrian Mihai Ionescu.
CHAPTER 5: Power Devices; Andrzej Napieralski, Malgorzata Napieralska and Lukasz Starzak.
CHAPTER 6: Distributed modeling approach applied to the IGBT; Patrick Austin and Jean-Louis Sanchez.
CHAPTER 7: Web Based Modeling Tools; Andrzej Napieralski, Lukasz Starzak, Bartlomiej Swiercz and Mariusz Zubert.
Apr 27, 2010
[mos-ak] MOS-AK/GSA Rome Workshop Press Release
MOS-AK/GSA Modeling Working Group Holds Workshop in Rome
Academic and Industrial Experts Share Their Latest Perspectives on
Compact Modeling and Verilog-A Standardization
http://www.gsaglobal.org/news/article.asp?article=2010/0426
Academic and Industrial Experts Share Their Latest Perspectives on
Compact Modeling and Verilog-A Standardization
http://www.gsaglobal.org/news/article.asp?article=2010/0426
in other sources:
http://www.marketwatch.com/story/mos-akgsa-modeling-working-group-holds-workshop-in-rome-2010-04-26?reflink=MW_news_stmp
http://ca.news.finance.yahoo.com/s/26042010/34/biz-f-business-wire-mos-ak-gsa-modeling-working-group-holds-workshop.html
http://www.forbes.com/feeds/businesswire/2010/04/26/businesswire138742381.html
http://www.finanznachrichten.de/nachrichten-2010-04/16725421-mos-ak-gsa-modeling-working-group-holds-workshop-in-rome-004.htm
http://it.tmcnet.com/news/2010/04/26/4750513.htm
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New IEEE EDS Senior Members
My warmest welcome to the new IEEE Senior Members of the EDS in April:
Alberto Adan, Carlos Araujo, M Scott Burroughs, Gerd Hechtfischer, Aaron Ho, Syed Islam, Ioannis Kymissis, Sungjae Lee, Xian Liu, M Madheswaran, Enrique Miranda, Michael Parker, Vijay Reddy, Sean Rommel, Nikita Ryskin, Nayanathara Sattiraju, Keyhan Sinai, Bhaskar Srinivasan, Munehiro Tada, Tsuyoshi Tanaka, Thy Tran, Mingwei Xu, Tetsuo Yamada
Alberto Adan, Carlos Araujo, M Scott Burroughs, Gerd Hechtfischer, Aaron Ho, Syed Islam, Ioannis Kymissis, Sungjae Lee, Xian Liu, M Madheswaran, Enrique Miranda, Michael Parker, Vijay Reddy, Sean Rommel, Nikita Ryskin, Nayanathara Sattiraju, Keyhan Sinai, Bhaskar Srinivasan, Munehiro Tada, Tsuyoshi Tanaka, Thy Tran, Mingwei Xu, Tetsuo Yamada
Apr 23, 2010
[mos-ak] MOS-AK/GSA Rome workshop on-line publications
MOS-AK/GSA Rome workshop on-line publications are available:
http://www.mos-ak.org/rome/
http://www.mos-ak.org/rome/
I would like to thank all MOS-AK speakers and poster presenters for
sharing their compact modeling competence, R&D experience and
delivering valuable MOS-AK presentations. I am sure, that our modeling
event in Rome was beneficial to all MOS-AK Workshop attendees.
Organization of our modeling event would not be possible without our
generous sponsor: Agilent Technologies, Micron and Micron Foundation
as well as the IEEE EDS, technical co-sponsor. I also would like to
personally acknowledge local organizers, in particular, Professors
Fernanda Irrera and Marco Balucani for their dedication, commitment.
My very special 'thank you' goes to Angela Gatto and Paolo Nenzi not
only for providing smooth workshop logistics.
I hope, we would have a next chance to meet all of you and your
academic and industrial partners at future MOS-AK/GSA modeling events
(listed below).
-- with regards - WG (for the MOS-AK/GSA)
==========================================================
* London: May 18-19, www.gsaglobal.org
* Tarragona: Jun.30-Jul.1 www.compactmodelling.eu/an_details.php?anID=14
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Seville: Sept. 17 www.mos-ak.org/seville http://www.essderc2010.org/
* San Francisco: Dec'10 www.mos-ak.org
==========================================================
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Apr 20, 2010
3rd International Workshop on Compact Thin-Film Transistor Modeling (C-TFT)
The 3rd International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation (C-TFT) will be held in Tarragona on July 2 2010.
The C-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London.
Topics:
A partial list of the areas of interest includes:
- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
Other details:
Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat
Important dates:
- Deadline for abstract submission: May 7, 2010
- Notification of acceptance: May 21, 2010
- Camera-ready version: Jun 18, 2010
This event will be held in coordination with the Training Courses on Compact Modeling (June 30-July 1) and the Graduate Student Meeting on Electronic Engineering (June 28-29).
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
The C-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London.
Topics:
A partial list of the areas of interest includes:
- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
Other details:
Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat
Important dates:
- Deadline for abstract submission: May 7, 2010
- Notification of acceptance: May 21, 2010
- Camera-ready version: Jun 18, 2010
This event will be held in coordination with the Training Courses on Compact Modeling (June 30-July 1) and the Graduate Student Meeting on Electronic Engineering (June 28-29).
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
Training Courses on Compact Modeling: June 30-July 1 2010
The first edition of the Training Courses on Compact Modeling (TCCM) will consist of a set of lectures addressing relevant topics in the compact modeling of advanced electron devices. Most of the courses will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.
The Training Courses on Compact Modeling will be held in Tarragona (Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).
The Training Courses on Compact Modeling are sponsored by the FP7 “COMON” IAPP Project and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.
The Training Courses on Compact Modeling will be especially suited to researchers from both industry and academia working on electron device modeling, circuit and systems design and electronic design automated tools. In particular, the courses will be very interesting and useful to students working on these topics.
The General Chair Person is Prof. Benjamin Iñiguez, Universitat Rovira i Virgili, Tarragona, Spain.
The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee.
Topics:
A total of 10 lectures will be conducted. Tthe final programme, with the timetable, will be available soon.
1. Tibor Grasser (TU-Wien) - Transport modeling
2. Tor A Fjeldly (UniK, Norway) - Analytical 2D and 3D electrostatic modeling
3. Jamal Deen (McMaster University, Canada) - Noise modeling
4. Benjamin Iniguez (URV, Spain) - Analytical small-signal modeling
5. Ilcho Angelov (Chalmers University, Sweden) - High frequency device modeling
6. Renaud Gillon (On Semiconductor, Belgium) - Electro-thermal and reliability modeling
7. Sorin Cristoloveanu (MINATEC and LETI, France) - Electrical characterization of SOI and Multi-Gate MOSFETs
8. Asen Asenov (University of Glasgow) - Statistical variability and corresponding compact model strategies
9. Kiyoh Itoh (Hitachi, Japan) - "Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs"
10. Wladek Grabinski - "GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization"
The Training Courses on Compact Modeling will be held in Tarragona (Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).
The Training Courses on Compact Modeling are sponsored by the FP7 “COMON” IAPP Project and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.
The Training Courses on Compact Modeling will be especially suited to researchers from both industry and academia working on electron device modeling, circuit and systems design and electronic design automated tools. In particular, the courses will be very interesting and useful to students working on these topics.
The General Chair Person is Prof. Benjamin Iñiguez, Universitat Rovira i Virgili, Tarragona, Spain.
The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee.
Topics:
A total of 10 lectures will be conducted. Tthe final programme, with the timetable, will be available soon.
1. Tibor Grasser (TU-Wien) - Transport modeling
2. Tor A Fjeldly (UniK, Norway) - Analytical 2D and 3D electrostatic modeling
3. Jamal Deen (McMaster University, Canada) - Noise modeling
4. Benjamin Iniguez (URV, Spain) - Analytical small-signal modeling
5. Ilcho Angelov (Chalmers University, Sweden) - High frequency device modeling
6. Renaud Gillon (On Semiconductor, Belgium) - Electro-thermal and reliability modeling
7. Sorin Cristoloveanu (MINATEC and LETI, France) - Electrical characterization of SOI and Multi-Gate MOSFETs
8. Asen Asenov (University of Glasgow) - Statistical variability and corresponding compact model strategies
9. Kiyoh Itoh (Hitachi, Japan) - "Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs"
10. Wladek Grabinski - "GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization"
Apr 7, 2010
The Semiconductor Industry’s Nanoelectronics Research Initiative: Motivation and Challenges
Part-2 in the IEEE SCV Electron Devices Society (EDS) "Semiconductor Roadmap and Beyond" series.
Speaker: Dr. Jeffrey Welser, Director, SRC Nanoelectronics Research Initiative
Time: TUESDAY, Apr 13, 2010 6:00 PM - Pizza , 6:15 PM – Lecture
Cost: Free
Location: National Semiconductor, Building E1, Conference Center ,
2900 Semiconductor Drive , Santa Clara , CA 95051 .
See the NSC Building location map and directions
Contact: Sandeep Bahl
Apr 6, 2010
Alliance CAD System
Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor: http://alliancecad.sourceforge.net
This project may now be found at http://www-asim.lip6.fr/recherche/alliance/.
Mar 25, 2010
IPL group releases PDK standard
What's next? Under this framework, OpenPDK will base its PDK technology on the OpenAcess database. It will also use several of the components developed by IPL: OA schematic symbols, component description format (CDF) and callbacks. For its part, Si2 will attempt to get the industry to develop standards around several other components: Spice models, tech files and DRC/LVS/LPE. [more]
Mar 22, 2010
Design, Test, Integration & Packaging of MEMS/MOEMS
DTIP 2010, 5-7 May 2010 , Seville, Spain
DTIP 2010 will be a follow-up to the very successful issues held in 1999 and 2000 in Paris and in 2001, 2002 and 2003 in Mandelieu-La Napoule, in 2004 and 2005 in Montreux, Switzerland in 2006, in 2007 in Stresa, Italy, in 2008 in Nice, France and in 2009 in Rome, Italy. This series of Symposia is a unique single-meeting event expressly planned to bring together participants interested in manufacturing microstructures and participants interested in design tools to facilitate the conception of these microstructures. Again, a special emphasis will be put on the very crucial needs of MEMS/MOEMS in terms of packaging solutions. The goal of the Symposium is to provide a forum for in-depth investigations and interdisciplinary discussions involving design, modeling, testing, micromachining, microfabrication, integration and packaging of structures, devices, and systems. The Symposium is sponsored by the IEEE Components, Packaging, and Manufacturing Technology Society and CMP.
DTIP 2010 will be a follow-up to the very successful issues held in 1999 and 2000 in Paris and in 2001, 2002 and 2003 in Mandelieu-La Napoule, in 2004 and 2005 in Montreux, Switzerland in 2006, in 2007 in Stresa, Italy, in 2008 in Nice, France and in 2009 in Rome, Italy. This series of Symposia is a unique single-meeting event expressly planned to bring together participants interested in manufacturing microstructures and participants interested in design tools to facilitate the conception of these microstructures. Again, a special emphasis will be put on the very crucial needs of MEMS/MOEMS in terms of packaging solutions. The goal of the Symposium is to provide a forum for in-depth investigations and interdisciplinary discussions involving design, modeling, testing, micromachining, microfabrication, integration and packaging of structures, devices, and systems. The Symposium is sponsored by the IEEE Components, Packaging, and Manufacturing Technology Society and CMP.
Download the call for participation.
Mar 21, 2010
Mar 19, 2010
Big Success in Dresden for new DATE 2010
The conference again proved its World-Wide leadership with attendees from 39 Countries. Germany accounts for a fourth of the attendees, followed by USA and France. China showed a substantial increase and was already number 4 of the participating countries. The number of attendees (1,300) again reached the very high level of the previous years [more].The proceedings of DATE10 are now available on-line.
Mar 17, 2010
[mos-ak] Final Program MOS-AK/GSA Workshop in Rome
Please visit the MOS-AK/Rome Workshop web site:
http://www.mos-ak.org/rome/ with final workshop program
http://www.mos-ak.org/rome/ with final workshop program
April 8-9, 2010 Sapienza Università di Roma
* Free On-line Registration Form:
http://www.mos-ak.org/rome/index.php#Register
* Venue and Recommended Hotels:
http://www.mos-ak.org/rome/index.php#Venue
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Mar 15, 2010
Angelov FET Model Documents at Uni.Chalmers
New web page with collection of some documents, files and papers on Angelov's FET Large Signal Nonlinear Transistor Mode [link]
Mar 5, 2010
Top 10 cited papers in Solid-State Electronics
I wish to congratulate some friends, because their papers are ranked 4th and 5th in the top 10 cited papers published in Solid-State Electronics... and these are also the first papers in the list about compact modelling...
Many congratulations Adelmo, Francisco, Jean-Michel and Christian !
By the way, the papers are:
Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs
Volume 49, Issue 4, 2005, Pp 640-647
Ortiz-Conde, A. | Sánchez, F.J.G. | Muci, J.
A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism
Volume 49, Issue 3, 2005, Pp 485-489
Sallese, J.-M. | Krummenacher, F. | Prégaldiny, F. | Lallement, C. | Roy, A. | Enz, C.
Many congratulations Adelmo, Francisco, Jean-Michel and Christian !
By the way, the papers are:
Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs
Volume 49, Issue 4, 2005, Pp 640-647
Ortiz-Conde, A. | Sánchez, F.J.G. | Muci, J.
A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism
Volume 49, Issue 3, 2005, Pp 485-489
Sallese, J.-M. | Krummenacher, F. | Prégaldiny, F. | Lallement, C. | Roy, A. | Enz, C.
Mar 2, 2010
Compact TFT Modelling Workshop (C-TFT)
The Third International Workshop on Compact Thin-Film Transistor Modelling (C-TFT) will be held in Tarragona, Spain, on July 2 2010.
This workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London .
Topics:
A partial list of the areas of interest includes:
- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
Other details:
Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat
Important dates:
- Deadline for abstract submission: May 7, 2010
- Notification of acceptance: May 21, 2010
- Camera-ready version: Jun 18, 2010
Technical comitee members:
General chair person: Prof. Benjamin Iniguez, University Rovira i Virgili, Spain
Rodrigo Picos, Universitat de les Illes Balears, Spain
Bill Milne, Cambridge University, UK
Maria Merlyne De Souza, Sheffield University, UK
Arokia Nathan, University College London, UK
Norbert Fruehauf, University of Stuttgart, Germany
Samar Saha, Silterra Corp., USA
Jamal Deen, McMaster University, Canada
Magali Estrada, CINVESTAV, Mexico
James B. Kuo, National Taiwan University, Taiwan
Hyun Jae Kim, Yonsei University, Korea
Zhou Xing, Nanyang Technological University, Singapore
Local Committee Members:
Benjamin Iniguez, Universitat Rovira i Virgili, Spain
Lluis F. Marsal, Universitat Rovira i Virgili, Spain
Josep Pallares, Universitat Rovira i Virgili, Spain
Josep Ferre, Universitat Rovira i Virgili, Spain
Roger Cabre, Universitat Rovira i Virgili, Spain
Pilar Formentin, Universitat Rovira i Virgili, Spain
Francois Lime, Universitat Rovira i Virgili, Spain
Bogdan Nae, Universitat Rovira i Virgili, Spain
Directions and maps:
University of Rovira i Virgili Campus Map
Tarragona is well connected with the spanish airports of Madrid, Barcelona or Reus by means of trains or buses.
For train tickets, please visit the national railroad company, RENFE. For bus information, please visit La Hispano Igualadina company.
About Tarragona:
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
This workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London .
Topics:
A partial list of the areas of interest includes:
- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
Other details:
Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat
Important dates:
- Deadline for abstract submission: May 7, 2010
- Notification of acceptance: May 21, 2010
- Camera-ready version: Jun 18, 2010
Technical comitee members:
General chair person: Prof. Benjamin Iniguez, University Rovira i Virgili, Spain
Rodrigo Picos, Universitat de les Illes Balears, Spain
Bill Milne, Cambridge University, UK
Maria Merlyne De Souza, Sheffield University, UK
Arokia Nathan, University College London, UK
Norbert Fruehauf, University of Stuttgart, Germany
Samar Saha, Silterra Corp., USA
Jamal Deen, McMaster University, Canada
Magali Estrada, CINVESTAV, Mexico
James B. Kuo, National Taiwan University, Taiwan
Hyun Jae Kim, Yonsei University, Korea
Zhou Xing, Nanyang Technological University, Singapore
Local Committee Members:
Benjamin Iniguez, Universitat Rovira i Virgili, Spain
Lluis F. Marsal, Universitat Rovira i Virgili, Spain
Josep Pallares, Universitat Rovira i Virgili, Spain
Josep Ferre, Universitat Rovira i Virgili, Spain
Roger Cabre, Universitat Rovira i Virgili, Spain
Pilar Formentin, Universitat Rovira i Virgili, Spain
Francois Lime, Universitat Rovira i Virgili, Spain
Bogdan Nae, Universitat Rovira i Virgili, Spain
Directions and maps:
University of Rovira i Virgili Campus Map
Tarragona is well connected with the spanish airports of Madrid, Barcelona or Reus by means of trains or buses.
For train tickets, please visit the national railroad company, RENFE. For bus information, please visit La Hispano Igualadina company.
About Tarragona:
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
Feb 26, 2010
Lots of Foundries and Fabless Companies do exist - what about standards for their interface?
DATE 2010 ET-P3 PANEL SESSION
Date: Thu, 2010-03-11; Time: 12:45-13:45
Room: Exhibition Theatre, Ground Floor
Organizers: Manfred Dietrich, Fraunhofer IIS/EAS, and Rene Schueffny, TU Dresden
Date: Thu, 2010-03-11; Time: 12:45-13:45
Room: Exhibition Theatre, Ground Floor
Organizers: Manfred Dietrich, Fraunhofer IIS/EAS, and Rene Schueffny, TU Dresden
Companies like Broadcom and Nvidia have shown that the Fabless model conquers the semiconductor market. Today all IDM’s use foundries as second source or use it as part of their volume production Because of the high cost of new manufacturing facilities IDM’s become Fablight and concentrate with their production on highly sophisticated processes. How is it possible to handle even more complex circuits if their processes cannot any more be deeply influenced by the internal design team? Today the value chain of the semiconductor market isolates and dominates more and more the vertical companies like EDA, Design house, Fabless, IP provider, Foundry Test & Packaging. Do we have already enough standards or do we need more and where do we need more standards and how can we make it happen? Who will be the driver or who should be the driver? This panel should offer some answers or even create more questions! It is fact - Fabless companies will have more and more impact in the whole IC logic market and Foundries increase their market share every year! Is it time for standards? [more]
Download DATE 2010 Conference Programme (PDF - 3 MB)
Download DATE 2010 Conference Programme (PDF - 3 MB)
Feb 24, 2010
Ultra Low Power Bioelectronics
Fundamentals, Biomedical Applications, and Bio-inspired Systems
Rahul Sarpeshkar; Massachusetts Institute of Technology
Hardback (ISBN-13: 9780521857277)
This book provides, for the first time, a broad and deep treatment of the fields of both ultra low power electronics and bioelectronics. It discusses fundamental principles and circuits for ultra low power electronic design and their applications in biomedical systems. It also discusses how ultra energy efficient cellular and neural systems in biology can inspire revolutionary low power architectures in mixed-signal and RF electronics. The book presents a unique, unifying view of ultra low power analog and digital electronics and emphasizes the use of the ultra energy efficient subthreshold regime of transistor operation in both. Chapters on batteries, energy harvesting, and the future of energy provide an understanding of fundamental relationships between energy use and energy generation at small scales and at large scales. A wealth of insights and examples from brain implants, cochlear implants, bio-molecular sensing, cardiac devices, and bio-inspired systems make the book useful and engaging for students and practicing engineers.
[Table of contents]
Rahul Sarpeshkar; Massachusetts Institute of Technology
Hardback (ISBN-13: 9780521857277)
[Table of contents]
Feb 19, 2010
Post-doctoral Research Positions in Healthcare Management
The newly established Collaboration in Healthcare Managemenat Ulm University in Germany invites applications for:
Two Full-Time Post-doctoral Research Positions in Healthcare Management
(or as part-time research/PhD positions for Master’s degree holders)*
Ulm University, a leading medical and natural sciences university in Germany, is seeking two post-doctoral candidates for the newly established collaboration in Healthcare Management. This concentration brings together the medical and the business school at Ulm University to develop expertise in healthcare management. The candidates will work directly for the newly appointed professor of healthcare management and controlling at Ulm University and contribute to developing the teaching and research program. Candidates will participate in domestic and international collaborations with leading academic and medical institutions. Ideal candidates will possess academic or practical healthcare management experience and an understanding of the healthcare market, but need not come from a healthcare background. Candidates can expect the position to open doors for healthcare administration in Europe and the U.S.
To apply: Please send CV, cover letter, a brief synopsis of a research project previously conducted (or up to three selected publications) and up to 3 letters of reference to Prof. Dr. Katharina Janus latest until March 11, 2010.
[more]
*Non-PhD holders:
Candidates without a PhD have the option to complete a PhD at Ulm University while working part-time in the described positions. The professor of health management and controlling will act as the PhD candidate’s academic supervisor. To enroll in the PhD, candidates need to hold a Master’s Degree in a related field and propose an adequate research topic to the academic supervisor.
Two Full-Time Post-doctoral Research Positions in Healthcare Management
(or as part-time research/PhD positions for Master’s degree holders)*
Ulm University, a leading medical and natural sciences university in Germany, is seeking two post-doctoral candidates for the newly established collaboration in Healthcare Management. This concentration brings together the medical and the business school at Ulm University to develop expertise in healthcare management. The candidates will work directly for the newly appointed professor of healthcare management and controlling at Ulm University and contribute to developing the teaching and research program. Candidates will participate in domestic and international collaborations with leading academic and medical institutions. Ideal candidates will possess academic or practical healthcare management experience and an understanding of the healthcare market, but need not come from a healthcare background. Candidates can expect the position to open doors for healthcare administration in Europe and the U.S.
To apply: Please send CV, cover letter, a brief synopsis of a research project previously conducted (or up to three selected publications) and up to 3 letters of reference to Prof. Dr. Katharina Janus latest until March 11, 2010.
[more]
*Non-PhD holders:
Candidates without a PhD have the option to complete a PhD at Ulm University while working part-time in the described positions. The professor of health management and controlling will act as the PhD candidate’s academic supervisor. To enroll in the PhD, candidates need to hold a Master’s Degree in a related field and propose an adequate research topic to the academic supervisor.
Feb 18, 2010
PhD Studentship Available in Scanning Probe Microscopy of Biomolecular Surfaces - Dublin, Ireland
Investigating Electrostatic Interactions in Biomolecular Systems at the Nanoscale
Nanoscale characterization of electric charge and electric surface potentials in biomolecular systems is critical for understanding biomolecular interactions. Changes in surface potential dictate cellular-membrane transport and thus provide a crucial pathway for cells to interact with their environment. This project will focus on investigating electrostatic interactions at biological surfaces using a scanning probe approach. Mapping electrostatic interactions in biological systems may provide a pathway to understand the role of charge in biological processes.
This interdisciplinary project will provide training in advanced ambient and liquid, structural and functional imaging using an atomic force microscope (AFM) and in biological sample preparation. The successful applicant will be involved in the further development of advanced scanning probe techniques and novel shielded AFM probes and is expected to develop and publish their work and to present their work at national and international conferences. He/She will have access to state of the art AFMs, and will be expected to work closely with the Nanoscale Function Group of Prof. Suzi Jarvis. Travel opportunities to interact with collaborating researchers and industrial partners are also envisaged.
Funding is available for up to 4 years and includes a stipend of €15k per annum, plus EUfees.Location: UCD Conway Institute of Biomolecular and Biomedical Research, Dublin, Ireland
Qualification: Candidates should have or expect to obtain a first or upper second BSc (or equivalent) or MSc in Physics, Materials Science, Biology, or a related area.
Funding is restricted to EU applicants only.
More information: http://www.nanopaprika.eu/profiles/blogs/phd-studentship-available-in
Nanoscale characterization of electric charge and electric surface potentials in biomolecular systems is critical for understanding biomolecular interactions. Changes in surface potential dictate cellular-membrane transport and thus provide a crucial pathway for cells to interact with their environment. This project will focus on investigating electrostatic interactions at biological surfaces using a scanning probe approach. Mapping electrostatic interactions in biological systems may provide a pathway to understand the role of charge in biological processes.
This interdisciplinary project will provide training in advanced ambient and liquid, structural and functional imaging using an atomic force microscope (AFM) and in biological sample preparation. The successful applicant will be involved in the further development of advanced scanning probe techniques and novel shielded AFM probes and is expected to develop and publish their work and to present their work at national and international conferences. He/She will have access to state of the art AFMs, and will be expected to work closely with the Nanoscale Function Group of Prof. Suzi Jarvis. Travel opportunities to interact with collaborating researchers and industrial partners are also envisaged.
Funding is available for up to 4 years and includes a stipend of €15k per annum, plus EUfees.Location: UCD Conway Institute of Biomolecular and Biomedical Research, Dublin, Ireland
Qualification: Candidates should have or expect to obtain a first or upper second BSc (or equivalent) or MSc in Physics, Materials Science, Biology, or a related area.
Funding is restricted to EU applicants only.
More information: http://www.nanopaprika.eu/profiles/blogs/phd-studentship-available-in
MIXDES 2010 paper submission deadline - less than 2 weeks left
I would like to kindly remind you that there is less than 2 weeks left for regular paper submission for MIXDES 2010 Conference. If you have any remaining papers which has not been submitted yet, I kindly ask you to do so before the deadline expiration.
Please note that the papers should be registered and submitted from the conference website (www.mixdes.org).
If you any problems with registration, please report it the MIXDES Conference Secretary (mixdes2010@dmcs.p.lodz.pl) ASAP.
Feb 15, 2010
Open Senior Researcher Position in Compact Device Modeling
A Senior Researcher position is offered in the Department of The Electronic, Electrical and Automatic Control Engineering in the Universitat Rovira i Virgili (Tarragona, Spain). This position has a duration of 5 years, with chances of obtaining a tenure as Associate Professor. It is funded by the prestigeous "Ramón y Cajal Programme" from the Spanish Ministry of Science and Innovation.
The candidate should have a Ph D in Electrical Engineering, Electronic Engineering, Telecommunication Engineering, Physics, or related disciplines. At least three years of postdoctoral experience are needed.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile, and it can be proposed by the candidate. In any case, it will be related to the National and European projects from which my group receives funding. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by those projects: thin-film SOI and multi-gate MOSFETs (FinFETs, DG MOSFETs, Gate All-Around MOSFETs), High Voltage MOSFETs, advanced HEMTs and Organic Thin Film Transistors (OTFTs).
The net salary will be around 2200 Euro/month. The position will include a research grant that the successful candidate can use to fund the beginning of his/her research.
Tarragona is a small city (110000 inhabitants) on the Mediterranean coast, about 100 Km south from Barcelona, and very well connected to Barcelona and the main Spanish cities by rail and highway. Tarragona is a very old city, very important during the Roman Empire, and with a lot of historical landmarks.
The quality of life in Tarragona is excellent. Mediterranean and mild climate the whole year. Wonderful beaches around the city (even at the city). Mountains close to the city (even the Pyrenees are not far). Besides, the city is very quiet, but with an intense nightlife.
My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling (in which a total of 15 European universities and companies participate). We also participate on two other European projects (two about nanoscale MOSFETs and another one about organic Thin Film Transistors).
Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: February 24 2010.
MY E-MAIL ADDRESS IS: benjamin.iniguez@gmail.com
Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona
SPAIN.
The candidate should have a Ph D in Electrical Engineering, Electronic Engineering, Telecommunication Engineering, Physics, or related disciplines. At least three years of postdoctoral experience are needed.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile, and it can be proposed by the candidate. In any case, it will be related to the National and European projects from which my group receives funding. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by those projects: thin-film SOI and multi-gate MOSFETs (FinFETs, DG MOSFETs, Gate All-Around MOSFETs), High Voltage MOSFETs, advanced HEMTs and Organic Thin Film Transistors (OTFTs).
The net salary will be around 2200 Euro/month. The position will include a research grant that the successful candidate can use to fund the beginning of his/her research.
Tarragona is a small city (110000 inhabitants) on the Mediterranean coast, about 100 Km south from Barcelona, and very well connected to Barcelona and the main Spanish cities by rail and highway. Tarragona is a very old city, very important during the Roman Empire, and with a lot of historical landmarks.
The quality of life in Tarragona is excellent. Mediterranean and mild climate the whole year. Wonderful beaches around the city (even at the city). Mountains close to the city (even the Pyrenees are not far). Besides, the city is very quiet, but with an intense nightlife.
My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling (in which a total of 15 European universities and companies participate). We also participate on two other European projects (two about nanoscale MOSFETs and another one about organic Thin Film Transistors).
Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: February 24 2010.
MY E-MAIL ADDRESS IS: benjamin.iniguez@gmail.com
Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona
SPAIN.
Feb 12, 2010
[mos-ak] MOS-AK/GSA Workshop in Rome // 2nd announcement
Please visit the MOS-AK/Rome Workshop web site:
http://www.mos-ak.org/rome/
http://www.mos-ak.org/rome/
with updated:
* Speakers list:
http://www.mos-ak.org/rome/index.php#Speakers
* Free On-line Registration Form:
http://www.mos-ak.org/rome/index.php#Register
* Venue and Recommended Hotels:
http://www.mos-ak.org/rome/index.php#Venue
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Feb 5, 2010
Job offers at GLOBALFOUNDRIES Singapore
I post here a job offer I've found, because it may interest someone...
If you wish to apply, you can go to the original website here. Good luck!!
Senior Engineer
Engineer
Requirements
Senior Engineer
Engineer
If you wish to apply, you can go to the original website here. Good luck!!
Senior Engineer
- Assist in the ESD and LU development support for various technology nodes
- The job scope will include extensive test chip design and layout, spice model development, circuit simulations, layout verification, design database preparation and documentation
- The job scope includes R&D on new and optimized ESD solutions from a foundry perspective
- In this position, the staff will be support cross functionally teams such as IO design and ESD library development
Other responsibilities will include: - Investigates and develops solution for highly complex circuit level ESD problems
- Learn and evolve in any other skills and tools required to achieve challenging ESD development goals including automation, and new research areas
- Publish in relevant peer reviewed journal and conferences
- Actively pursue patent development
Engineer
- The engineer will actively pursue ESD device development and assessment of ESD and LU performance of various technologies
- The responsibilities include device definition, characterization of the ESD devices using DC, pulsed and RF testers, latch up characterization, documentation and reporting, assist internal process owners for the ESD and LU rule definition
Other responsibilities include: - As required, explore the need to modify any given processes, procedures or methods to develop new solutions for the foundry and its customers
- Continuously research and potentially develop new test methods and charactersation approaches.
- Publish in relevant peer reviewed journal and conferences
- Actively pursue patent development
Requirements
- Phd or Masters Degree in Physics
- 2 to 5 years of relevant working experience
Senior Engineer
- Good and demonstrated knowledge in device layout, circuit design, custom layout, and IO design
- Well versed in circuit design and layout tools (such as those from cadence or Mentor)
- Analog circuit and RF design knowledge is a plus
Engineer
- Good knowledge of microelectronics and semiconductor device physics
- Demonstrated expertise and knowledge in ESD protection design and analysis using pulsed/ ESD testers, and device design
- Experience in HV device physics, compact model simulation, and product engineering is valuable
- Candidate is required to have exceptional technical skills combined with evidence of motivation to work in ESD and LU reliability area
- Open and willing to listen to internal and external customer concerns and willing to go an extra mile to help customers succeed in their efforts to achieve required ESD and LU performance targets
- Fluency in English language is a must, with good comprehension capability
- Ability to handle anyone with a pleasant attitude and willingness to share/mentor colleagues
DATE 2010 Advance Programme is Available
DATE10 Programme
Download Conference Programme (PDF - 3 MB)
Download Fringe Meetings Programme (PDF - Coming soon)
Event Overview
Download Conference Programme (PDF - 3 MB)
Download Fringe Meetings Programme (PDF - Coming soon)
Event Overview
Feb 1, 2010
2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - Call For Papers
2010 BIPOLAR/BiCMOS CIRCUITS AND TECHNOLOGY MEETING Austin, Texas, USA http://www.ieee-bctm.org Short Course: Monday October 4, 2010, Conference: Tuesday and Wednesday October 5-6, 2010 Modeling Workshop: Thursday October 7, 2010 The Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) is a forum for technical communication focused on the needs and interests of the bipolar and BiCMOS community. Papers covering the design, performance, fabrication, testing and application of bipolar and BiCMOS integrated circuits, bipolar phenomena, and discrete bipolar devices are solicited. All papers must be suitable for a twenty-minute presentation. Text and figures must not have been presented at other conferences or published in any scientific or technical publications prior to BCTM. Publication in the BCTM 2010 Proceedings does not preclude publication in an IEEE journal, and authors are encouraged to do so. A Special Issue of the IEEE Journal of Solid-State Circuits will include selected papers from BCTM 2010.
Papers are solicited in the following areas: - ANALOG / DIGITAL CIRCUIT DESIGN - RADIO FREQUENCY CIRCUIT DESIGN - WIRELINE COMMUNICATIONS: LAN, WAN, FDDI - DEVICE PHYSICS - MODELING / SIMULATION- PROCESS TECHNOLOGY STUDENT PAPERS ARE ENCOURAGED If you know of people who may have a paper to contribute please bring this Call for Papers to their attention. IMPORTANT DEADLINES FOR AUTHORS Monday, May 3, 2010 Deadline for receipt of abstract and summary Friday, June 11, 2010 Notification of acceptance to be sent by email Friday, July 23, 2010 Final proceedings manuscript due SUBMISSION AND CONTACT INFORMATION Visit the conference website: www.ieee-bctm.org, or contact: Jan Jopke, Conference Manager, CCS Associates, 6611 Countryside Drive, Eden Prairie, MN 55346, USA TEL: 1-952-934-5082, FAX: 1-952-934-6741 E-mail: ccsevents@comcast.net.
Jan 26, 2010
A paper in the Feb. issue of IEEE TED
| A Physically Based Accurate Model for Quantum Mechanical Correction to the Surface Potential of Nanoscale MOSFETs Karim, M. A. Haque, A. Department of Electrical and Electronic Engineering, United International University, Dhaka; This paper appears in: Electron Devices, IEEE Transactions on Publication Date: Feb. 2010 Volume: 57, Issue: 2 On page(s): 496-502 ISSN: 0018-9383 Digital Object Identifier: 10.1109/TED.2009.2037453 First Published: 2009-12-28 Current Version Published: 2010-01-19 |
 |
|
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| Abstract |
Analog FastSpice RF delivers noise analysis for RF circuits
By Rick Nelson, Editor-in-Chief -- EDN, 12/22/2009
Berkeley Design Automation Inc has announced AFS RF (Analog FastSpice radio frequency), which Chief Operating Officer Paul Estrada calls the industry’s first true Spice-accurate noise-analysis tool for RF circuits. AFS RF accurately analyzes nanometer-scale device noise impact for all types of prelayout and postlayout circuits, ensuring early insight into its impact on performance, power, and area.Before the emergence of AFS RF, designers had to use limited-spectrum RF tools that can only approximate device noise impact on RF circuits, Estrada explains. Such approximations are increasingly inaccurate with decreasing process geometries, often becoming grossly inaccurate in nanometer-scale circuits. Circuits with sharp transitions, such as switched-capacitor filters, charge pumps, and dividers; high-frequency circuits, such as RF front-end blocks; and oscillators are especially sensitive to these inaccuracies. Without accurate analysis, designers must include expensive design margin or risk missing specifications in silicon.
Using the industry’s first full-spectrum device-noise-analysis engine, Analog FastSpice RF provides true Spice accuracy for every run. For complex circuits, it is five to 10 times faster than traditional RF tools that can only approximate device-noise effects. AFS RF features the DNA (device noise-analysis) Advisor to characterize DNA requirements, high-capacity periodic-steady-state analysis for greater than 100,000-element postlayout circuits, full-spectrum periodic-noise analysis with true Spice accuracy, full-spectrum total oscillator-device-noise analysis capability with phase and amplitude noise, and harmonic balance for fast single-tone analysis of moderately nonlinear circuits.
You can read the full post here...
Jan 25, 2010
EAMTA 2010 / CAMTA - CUMTA 2010
EAMTA 2010 [www.eamta.com.ar]
The fifth School of Micro and Nanoelectronics will take place from October 1 - 9, 2010, in the facilities of Instituto de IngenierÃa Eléctrica of Universidad de la República del Uruguay and Departamento de IngenierÃa Eléctrica Universidad Católica del Uruguay.
CAMTA - CUMTA 2010 [www.eamta.com.ar]
The Conference section of the School will take place on Thursday October 7 and Friday October 8, 2010. All papers will be presented in poster format, to stimulate discussion and feedback. Tutorials will be in charge of distinguished lecturers.
Contact Information: For the 2010 edition of EAMTA, Dr. Fernando Silveira and Dr. Alfredo Arnaud will be the General Chairs: [eamta.ar (at) gmail.com]
The fifth School of Micro and Nanoelectronics will take place from October 1 - 9, 2010, in the facilities of Instituto de IngenierÃa Eléctrica of Universidad de la República del Uruguay and Departamento de IngenierÃa Eléctrica Universidad Católica del Uruguay.
CAMTA - CUMTA 2010 [www.eamta.com.ar]
The Conference section of the School will take place on Thursday October 7 and Friday October 8, 2010. All papers will be presented in poster format, to stimulate discussion and feedback. Tutorials will be in charge of distinguished lecturers.
Contact Information: For the 2010 edition of EAMTA, Dr. Fernando Silveira and Dr. Alfredo Arnaud will be the General Chairs: [eamta.ar (at) gmail.com]
Jan 24, 2010
ISSCC 2010 Preview: Assessing '05 predictions
A couple of safe ISSCC'05 bets reviewd by Don Scansen. Have ISSCC organizers learned something by looking back?
Agilent Technologies Announces YouTube Channel for Agilent EEsof EDA
Agilent Technologies Inc. has announced the launch of the Agilent EEsof EDA channel on YouTube. The channel features more than 100 informational videos with subtitles in 50 different languages. The videos offer detailed application information on the Advanced Design System, Genesys, SystemVue, and other electronic design automation software from Agilent EEsof. The channel is designed to provide tutorial information to Agilent’s large installed base of users, or to anyone wanting to learn more about Agilent EEsof’s design software and high-frequency design applications. [more]
Jan 21, 2010
Some papers
I've seen five interesting papers in the current issue of the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields (Volume 23, Issue 2, 2010.):
Pages: 88-106
Implementation of the symmetric doped double-gate MOSFET model in Verilog-A for circuit simulation JoaquÃn Alvarado, Benjamin Iñiguez, Magali Estrada, Denis Flandre, Antonio Cerdeira http://www3.interscience.wiley.com/journal/122527099/abstract Published Online: 30 Jul 2009 DOI: 10.1002/jnm.725 Pages: 107-126 New RF extrinsic resistances extraction procedure for deep-submicron MOS transistors J. C. Tinoco, J.-P. Raskin http://www3.interscience.wiley.com/journal/122581374/abstract Published Online: 1 Sep 2009 DOI: 10.1002/jnm.726 Pages: 127-139 Modelling CoolMOSC3 transistor characteristics in SPICE Krzysztof Górecki, Janusz Zar?bski http://www3.interscience.wiley.com/journal/122580694/abstract Published Online: 1 Sep 2009 DOI: 10.1002/jnm.727 Pages: 140-150 The compact d.c. electrothermal model of power MOSFETs for SPICE Janusz Zar?bski http://www3.interscience.wiley.com/journal/122582111/abstract Published Online: 1 Sep 2009 DOI: 10.1002/jnm.728 Pages: 151-163 Simple and accurate approaches to implement the complex trans-conductance suited for time-domain simulators for small-signal and large-signal table-based models Seyed Majid Homayouni, Dominique Schreurs, Bart Nauwelaers http://www3.interscience.wiley.com/journal/123242581/abstract Published Online: 15 Jan 2010 DOI: 10.1002/jnm.740
Jan 20, 2010
MIXDES 2010 paper submission deadline
The deadline for the MIXDES paper registration passes in approximately in 6 weeks (Feb 28th, 2010). The most current information about the conference, regular and special sessions invited talks etc. can be found at the in the Final Call for Papers.This year the conference will be organized in Wroclaw, one of the oldest and most beautiful cities in Poland. It is located in southwestern Poland, 160 km from Germany and 120 km from the Czech Republic. It is well equipped with communication facilities: international airport, railways and highways, so is quite easy to get there.
As in previous years the papers should be prepared following the paper formatting requirements, however the format may be corrected till the final paper versions deadline (May 15th, 2010). The paper registration and updates should be proceeded by your personal account at the conference web page after log on.
With further questions please contact Dr. Mariusz Orlikowski, the MIXDES 2010 Conference Secretary.
MIXDES Invited Talk
Let me inform you, that the invited talk "/Ultra-thin Body SOI and Nanowire Transistors for 22nm Technology Node and Below/ " by Thierry Poiroux (Commissariat à l'Énergie Atomique, France) is announced to be held at the MIXDES'2010 Conference (http://mixdes.org/Invited_papers.htm). It could (will) be very interesting.
Jan 16, 2010
Open Positions for Doctoral/Master Students on Particle Simulations of Nanostructures
at the Institute for Microelectronics, Vienna University of Technology.
Send your CV to apply@iue.tuwien.ac.at. The call is open until filling the positions.
Send your CV to apply@iue.tuwien.ac.at. The call is open until filling the positions.
ERC Advanced Grant an Siegfried Selberherr für Spin-Forschung
Siegfried Selberherr, Professor am Institut für Mikroelektronik der Technischen Universität (TU) Wien, wird als erster Ingenieur Österreichs mit dem „Advanced Grant“ des Europäischen Forschungsrats ERC (European Research Council) ausgezeichnet. Diese prestigeträchtige Auszeichnung ist mit einem Preisgeld von 1,7 Mio. Euro verbunden. Mit den Advanced Investigator Grants hat der ERC eine Förderschiene geschaffen, die sich an bereits etablierte WissenschafterInnen wendet. Mit den Mitteln sollen außergewöhnlich erfolgreiche ForscherInnen dazu ermutigt werden, ambitionierte Projekte mit interdisziplinärem Charakter in Angriff zu nehmen. Es gibt insgesamt sechs österreichische Staatsbürger, die mit einem Advanced Grant ausgezeichnet wurden, wobei nur vier davon in Österreich forschen. Weiters haben drei ausländische Forscher, die in Österreich tätig sind, einen Advanced Grant erhalten. [mehr]Jan 14, 2010
7th International Workshop on Compact Modeling Advance Program
Taipei International Convention Center (TICC)
Taipei, Taiwan
January 18, 2010
Advance Program available on-line
Taipei, Taiwan
January 18, 2010
Advance Program available on-line
Jan 12, 2010
Job offer (PhD grant)
Title: Integrated circuit behaviour optimization based on predictive test
Conditions:
- Duration three years ( it could be extended to a fourth year)
- Salary 1300 € per month plus medical insurance
- Support for attending conferences
- Free registration in the Electronic Engineering Master courses, shared between the UIB and the UPC (see the web)
Requirements of the candidates:
- Graduate on Electronic Engineering, Physics or equivalent.
- Interested in developing a career in research
Contact: Prof. Eugenio Garcia Moreno (eugeni.garcia in the server uib.es)
The call is expected to occur in January 2010, but you can find information about the previous call (2009) about deadlines, conditions, requisites, etc. in this page.
Summary:
Advances in manufacturing technologies of CMOS integrated circuits have enabled obtaining the shrinkage of the device dimensions together with higher working frequencies at the expense of a greater dispersion in their characteristics. The impact of process variations specially affects the performance specifications of the analog and RF sections.
The main objective of this project is to develop design methods that allow to construct inherently robust circuits against manufacturing process variations. We intend to approach the problem from previous results already obtained by our group in predictive test. This test strategy consists in estimating the circuit performance parameters from indirect measurements, an approach easier to implement than by means of the standard methods.
The proposed solution consists, first, in implementing the elements to carry out the test process on the own chip; this is the well-known Built in Self Test technique. Then, the results of the predictive test are used to modify, either the value of a circuit element or the own structure of the circuit, with the aim of optimizing some of their performance specifications. Hence, self-adjustable or reconfigurable circuits are obtained.
Although the concept can be applied to any anlog circuit, its implementation has to be tailored for each kind of circuits. Initially it will be applied to two circuits: a low pass filter for a RF receiver (self-tuning) and a pipeline analog to digital converter (reconfiguration). Nevertheless, all through the project we will seek new objective circuits.
Conditions:
- Duration three years ( it could be extended to a fourth year)
- Salary 1300 € per month plus medical insurance
- Support for attending conferences
- Free registration in the Electronic Engineering Master courses, shared between the UIB and the UPC (see the web)
Requirements of the candidates:
- Graduate on Electronic Engineering, Physics or equivalent.
- Interested in developing a career in research
Contact: Prof. Eugenio Garcia Moreno (eugeni.garcia in the server uib.es)
The call is expected to occur in January 2010, but you can find information about the previous call (2009) about deadlines, conditions, requisites, etc. in this page.
Summary:
Advances in manufacturing technologies of CMOS integrated circuits have enabled obtaining the shrinkage of the device dimensions together with higher working frequencies at the expense of a greater dispersion in their characteristics. The impact of process variations specially affects the performance specifications of the analog and RF sections.
The main objective of this project is to develop design methods that allow to construct inherently robust circuits against manufacturing process variations. We intend to approach the problem from previous results already obtained by our group in predictive test. This test strategy consists in estimating the circuit performance parameters from indirect measurements, an approach easier to implement than by means of the standard methods.
The proposed solution consists, first, in implementing the elements to carry out the test process on the own chip; this is the well-known Built in Self Test technique. Then, the results of the predictive test are used to modify, either the value of a circuit element or the own structure of the circuit, with the aim of optimizing some of their performance specifications. Hence, self-adjustable or reconfigurable circuits are obtained.
Although the concept can be applied to any anlog circuit, its implementation has to be tailored for each kind of circuits. Initially it will be applied to two circuits: a low pass filter for a RF receiver (self-tuning) and a pipeline analog to digital converter (reconfiguration). Nevertheless, all through the project we will seek new objective circuits.
Jan 11, 2010
The Children of Cyberspace
"The Children of Cyberspace: Old Fogies by Their 20s" By Brad Stone:
My 2-year-old daughter surprised me recently with two words: “Daddy’s book.” She was holding my Kindle electronic reader [continue reading]
My 2-year-old daughter surprised me recently with two words: “Daddy’s book.” She was holding my Kindle electronic reader [continue reading]
Jan 9, 2010
Ph D student fellowship in semiconductor device modeling
There is an open call for international fellowships to pursue a Ph D in Spain (the so-called "Becas MAE-AECID" from the Spanish Ministry of Foreign Affairs and Cooperation).
We want to get one fellowship for a Ph D student position in the Department of Electronic Engineering in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona , Spain. The subject of the Ph D would be o the development of new techniques of characterization and modeling of nanoscale semiconductor devices, in particular III-V transistors. It will be related to two European projects in which the hosting group participates.
The duration of the grant will be 4 years. The monthly salary will be 1000 Euro/month.
Candidates cannot be Spanish citizens nor residents in Spain. However, it is required that they
have at least a basic knowledge of the Spanish language.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.
Applicants must send to my e-mail address (benjamin.iniguez@gmail.com), and by January 17 2010, a CV together with
a copy of the academic certificates indicating the grades obtained for all subjects during their studies.
Tarragona is a medium city (100000 inhabitants) with a pleasant Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport.
My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling of semiconductor devices (in which a total of 15 European universities and companies participate).
Additional information about the University and the department can be found at: http://www.urv.cat/ and sauron.etse.urv.es.
We want to get one fellowship for a Ph D student position in the Department of Electronic Engineering in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona , Spain. The subject of the Ph D would be o the development of new techniques of characterization and modeling of nanoscale semiconductor devices, in particular III-V transistors. It will be related to two European projects in which the hosting group participates.
The duration of the grant will be 4 years. The monthly salary will be 1000 Euro/month.
Candidates cannot be Spanish citizens nor residents in Spain. However, it is required that they
have at least a basic knowledge of the Spanish language.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.
Applicants must send to my e-mail address (benjamin.iniguez@gmail.com), and by January 17 2010, a CV together with
a copy of the academic certificates indicating the grades obtained for all subjects during their studies.
Tarragona is a medium city (100000 inhabitants) with a pleasant Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport.
My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling of semiconductor devices (in which a total of 15 European universities and companies participate).
Additional information about the University and the department can be found at: http://www.urv.cat/ and sauron.etse.urv.es.
Jan 8, 2010
Semiconductors: Today & Tomorrow
Semiconductors: Today & Tomorrow is a cycle of seminars, running from January to June 2010, that bring a closer insight about trends, challenges and opportunities in semiconductor technology. Presented by expert, industry professionals the seminars seek to inspire and motivate students and professors alike into new areas of research and development, and to foster an entrepreneurial spirit that looks at emerging opportunities in the industry.
Registration on-line
Registration on-line
Jan 7, 2010
[mos-ak] C4F MOS-AK/GSA Rome Workshop
C4F MOS-AK/GSA Workshop: http://www.mos-ak.org/rome/
The IEEE Electron Devices Society is sponsoring coming MOS-AK/GSA
Workshop to be held in cooperation with the Faculty of Engineering,
Sapienza Università di Roma. The MOS-AK/GSA Workshop is HiTech forum
to discuss the frontiers of the electron devices modeling with
emphasis on simulation-aware models. Original papers presenting new
developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on Feb. 15, 2010
http://www.mos-ak.org/rome/abstracts.php
Selected best MOS-AK papers will be published in a special issue of
the Microelectronics Journal:
http://www.elsevier.com/wps/find/journaldescription.cws_home/405904/description#description
Further details and updates: http://www.mos-ak.org/rome/
==========================================================
* Tarragona: June'10 www.compactmodelling.eu
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Seville: Sept. 18 www.mos-ak.org
==========================================================
Jan 4, 2010
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