Sedemos News

Execs gather at SEMI ISS

2012-01-27T07:30:00.001-08:00

From Semiconductor Manufacturing and Design:

At SEMI's Industry Strategy Symposium (ISS), Applied Materials CEO Mike Splinter urged creation of a forum for equipment makers to provide input to the Global 450 Consortium (G450C). Splinter said collaboration is needed to tackle the 450mm transition, which could have an R&D t tag of $15-20 billion.

Speaking at ISS, an ASML executive put some hard numbers on the expected performance of the forthcoming commercial EUV tool. The NXE:3300 EUV scanners will start out with throughput rated at 69 wafers an hour, said James Koonmen.

The chip industry's three biggest spenders are bullish. Intel said it will up its capex spending for 2012, with more than a third of the $12.5 billion going into 14nm fab construction in Oregon and Arizona. Intel also promoted a manufacturing executive, Brian Krzanich, to chief operating officer, as part of a wider reorganization.

TSMC chairman Morris Chang said much of the foundry's $7 billion in 2012 capex is going into building new fabs in Taichung and Hsinchu, in preparation for 20nm risk production late next year. Samsung also is spending heavily, with capital expenditures of $29 billion going into making semiconductors and displays for mobile systems. More than a billion dollars is expected to go toward expanding logic IC capacity at its Austin fab.

KLA-Tencor said it has done a grounds-up redesign of its 2900 broadband wafer inspection tool, and upgraded its narrowband and e-beam wafer inspection systems as well.

SemiMD senior editor Mark LaPedus reported "there are more rumors that Micron Technology Inc. will make a bid for debt-ridden Elpida Memory Inc."

[mos-ak] C4P MOS-AK/GSA Workshop at JIIT, Noida (U.P.) India, March 16-18, 2012

2012-01-20T07:54:00.000-08:00

C4P MOS-AK/GSA Workshop at JIIT, Noida (U.P.) India, March 16-18,
2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop at
JIIT, Noida (U.P.) India, March 16-18, 2012 with the tutorial on CMOS
technology and SPICE Models by Dr. N.D. Arora, Silterra, Malaysia.

List of the international modeling experts contributing to the MOS-AK/
GSA Workshop includes following names (in alphabetic order)
* Nanrian D. Arora, Silterra, Malaysia
* Navakanta Bhat, IISC Bangalore, India
* A.B. Bhattacharyya, JIIT Noida, India
* Mike Brinson, London Metropolitan University, UK
* Amitava Dasgupta, IIT Chennai, India
* Christian Enz, EPFL, Switzerland
* Tamilmani Ethirajan, IBM, India
* Thomas Gneiting, ADMOS, Germany
* Wladek Grabinski, MOS-AK/GSA
* Andre Juge, STM, France
* M. Jagdesh Kumar, IIT Delhi, India
* Shantanu Mahapatra, IISc, India
* Mitiko Miura-Mattausch, Hiroshima University, Japan
* Ramgopal Rao, IIT Mumbai
* Samar Saha, IEEE
* Manoj Saxena, University of Delhi, India
* Ehrenfried Seebacher, AMS, Austria
* Vaidyanathan Subramanian, IBM, India
* Xing Zhou, NTU, Singapore

The terms of participation:
* To register please visit the INAE website <http://inae.org/
seminar.htm> and complete the registration form
* Poster abstract submission with the deadline on Jan. 31, 2012.
Posters' abstract of maximum 300 words and paper of maximum 5 pages in
A4 size double spaced two columns should be submitted to Prof. AB
Bhattacharyya at <inaehq@gmail.com>

Intending participants and authors should also note the following
deadlines:
* Announcement and Call for Papers - Q4 2012
* Poster abstract submission deadline - Jan.31, 2012
* Final Workshop Program - Feb. 2012
* MOS-AK/GSA Workshop - March 16-18, 2012

Further details and updates: <http://www.mos-ak.org/india>
Email contact: <india@mos-ak.org>

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[mos-ak] MOS-AK/GSA Washington DC on-line publications

2012-01-11T08:26:00.001-08:00

MOS-AK/GSA Washington DC workshop on-line publications are available,
visit:
http://mos-ak.org/washington_dc/

I would like to thank all MOS-AK/GSA speakers for sharing their
compact modeling competence, R&D experience and delivering valuable
MOS-AK/GSA presentations. I am sure, that our modeling event in
Washington DC was a beneficial on to all the attendees as well as to
all MOS-AK/GSA Group.

I hope, we would have a next chance to meet us with your academic and
industrial partners at future MOS-AK/GSA modeling events (check the
list below).

- with regards - WG (for the MOS-AK/GSA Committee)
––––––––––––––––––––––––––––––––––----------------
http://mos-ak.org/committee.html
––––––––––––––––––––––––––––––––––----------------
MOS-AK/GSA India March 16-17, 2012
<http://mos-ak.org/india/>
MOS-AK/GSA Dresden April 26-27, 2012
<http://mos-ak.org/dresden/>
MIXDES Special Modeling Sesion Warsaw May 24-26, 2012
<https://www.mixdes.org/Special_sessions.htm>
MOS-AK/GSA Bordeaux Sept.21, 2012
<http://goo.gl/bUrsp>
MOS-AK/GSA San Francisco Q4 2012
––––––––––––––––––––––––––––––––––----------------

EPFL Post-doctoral/ experienced engineer position

2012-01-11T03:02:00.000-08:00

Candidate will integrate the Swiss CTI project CAPED for a period of 18 months. This research project aims at developing new technologies based on low power wireless communications, for communication between one intelligent pill implanted in the digestive system and an external control unit. The main industrial partner of this project is the Swiss company Motilis Medica SA. Dr. Catherine Dehollain (RF IC group leader) is the scientific coordinator of this project.

We are looking for one post-doc/ experienced engineer specialized in low power microelectronic integrated circuits with strong practical experience in the following topics:

Design of CMOS low power integrated circuits (analog, mixed-mode and RF blocks)
Design of CMOS low power integrated circuits for energy scavenging (AC to DC converter, voltage regulator, bandgap reference circuit, power-on-reset circuit, etc)
Design of CMOS power management circuits
Design of CMOS low power transmitter and receiver (LNA, PLL, VCO, mixer, filters, etc) for wireless communications
Practical experience in the measurements of CMOS integrated circuits EDA tools dedicated to the design of integrated circuits (e.g. Cadence, Agilent ADS, Pspice, etc)

The RF IC group provides a stimulating environment, good working conditions, and collaborations within a team of 10 researchers and PhD students working on related projects.

Starting date: as soon as possible.
Contract duration: 18 months

Application has to include a CV, copies of the diplomas, significant published or unpublished papers, motivation letter and three letters of reference (or submit 3 reference names). Please send your application at the latest at the end of February 2012 to Dr. Catherine Dehollain

C4P: 2012 IEEE Silicon Nanoelectronics Workshop

2012-01-09T11:19:00.000-08:00

Hilton Hawaiian Village in Honolulu, Hawaii (June 10-11, 2012)
Sponsored by the IEEE Electron Device Society

Authors are encouraged to submit a full-length paper to the IEEE Transactions on Nanotechnology or the IEEE Transactions on Electron Devices.Download the Call for Papers (PDF format)Further InformationThe 2012 Silicon Nanoelectronics Workshop is a satellite workshop of the 2012 VLSI Symposia sponsored by the IEEE Electron Device Society. It will be held on June 10-11, 2012 at the Hilton Hawaiian Village in Honolulu, Hawaii USA. This will be the seventeenth workshop in the annual series. Original papers on nanometer-scale devices and technologies which utilize silicon or which are based on silicon substrates are welcome.Prospective authors are requested to submit an abstract in PDF format, consisting of one page of text and one page of figures. It must include the paper title, the authors’ names and affiliation(s), and the full contact information (mailing address, phone and FAX numbers, e-mail address) for the corresponding author. Accepted abstracts will be reproduced in the workshop proceedings exactly as received. Some of the accepted papers will be presented in Poster Sessions. The deadline for receipt of abstracts is 5PM (Pacific Time) April 1, 2012. Authors will be notified by April 30, 2012.

Registration forms and hotel reservation forms will be provided in the Advanced Program of the 2012 VLSI Technology Symposium (http://www.vlsisymposium.org/index.html).
Scope:
•Sub-10 nm transistors, including those employing non-classical structures, novel channel and source/drain materials, or non-thermal injection mechanisms
•Junction and insulator materials and process technology for nanoelectronic devices
•Techniques for fabrication of nanostructures, including nanometer-scale patterning
•Physics of nanoelectronic devices, e.g. quantum effects, non-equilibrium transport
•Modeling/simulation of nanoelectronic devices, e.g. including atomistic effects
•Nanoscale surface, interface, and heterojunction effects in devices
•Device scaling issues including doping fluctuations and atomic granularity
•Circuit design issues and novel circuit architectures, including quantum computing, for nanoelectronic devices
•Optoelectronics using silicon nanostructures
•Techniques targeting zero power electronics (self-supplying), including wireless sensors, energy harvesting, steep slope devices, ultra-low power design and devices
•Devices for heterogeneous integration on silicon, including Graphene, III-V devices, CNT, spin-based devices, MEMs and NEMS, etc.
[read more...]

Price per transistor on a chip

2012-01-03T07:08:00.000-08:00

The price per transistor on a chip has dropped dramatically since Intel was founded in 1968. Some people estimate that the price of a transistor is now about the same as that of one printed newspaper character.

Intel has shipped over 200 million CPUs using high-k/metal-gate transistors – the kind used in 32nm processors -- since the technology was first put into production in November 2007. This translates to over 50,000,000,000,000,000 (50 quadrillion) transistors, or the equivalent of over 7 million transistors for every man, woman and child on earth. [more]

25th ICMTS Conference

2012-01-03T07:05:00.000-08:00

SAN DIEGO March 19-22, 2012

Day 1	Day 2	Day 3
08:45 Registration	09:00 Registration	09:00 Registration
08:45 Welcome	09:00 Process Characterization	09:00 Matching
08:55 Design Margin	11:10 RF	10:50 Capacitance
10:45 Variability	12:10 ICMTS 2013	12:10 Closing
11:45 Exhibitor Presentation	13:50 Parameter Extraction
13:45 MEMS	16:00 Stress
15:55 Poster

Note: This program is subject to change without notice. Final printed version of program will be available at the conference.

Scientific employee, PhD student, or postdoc at TU Dresden

2012-01-03T05:14:00.000-08:00

in circuit design

on organic, flexible, roll-to-roll-printed & plastic-based semiconductor technologies

The period of employment is governed by the Fixed Term Research Contracts Act (Wissenschaftszeitvertragsgesetz - WissZeitVG). The position is in the frame of the FLEXIBILITY (Flexible Multifunctional Bendable Integrated Light-Weight Ultra-Thin Systems) project funded by the EU involving 7 industry partners and 4 research institutions. PhD students will find excellence prerequisites for an innovative PhD thesis. The first wireless communication receiver fully integrated in a piece of plastic foil (without the need for a silicon chip) will be developed. The project is coordinated by our chair and provides an excellent platform for interdisciplinary cooperation with industry partners.

Tasks:

Design (analyses, simulation, device modelling, layout, testing and documen-tation) of circuits and systems operating up to radio frequencies in novel OLAE (Organic and Large Area Electronics) and roll-to-toll printed technologies for wireless communications. The authoring of scientific publications and the participation at project meetings and international conferences are expected. The active involvement in project management is planned for postdocs.

Requirements:
Excellent to good master, Dipl.-Ing. or PhD degree in microelectron-ics, electrical engineering, physics or chemistry. Knowledge in circuit design, inde-pendent and flexible working attitude, innovative and analytical thinking, strong commitment, communicative team-player, good English. Knowledge in the following areas is advantageous: Integrated circuit design, OLAE, device modelling, high frequency engineering, communications and semiconductor technologies, measure-ment techniques, German language.
Miscellaneous:
Applications from women are particularly welcome. The same applies to the disabled. Interested candidates are requested to submit concise application material including CV and copy of certificates per email in pdf format to Frank.Ellinger@tu-dresden.de [read more...]

Trends confirming IEDM (by Jerzy Ruzyllo)

2011-12-22T01:31:00.000-08:00

Fresh from IEDM, my [JR] first thought is that it continues to be a great forum to interact with people speaking the same language (language of semiconductors, that is), to refresh all contacts, and to establish new ones. And that's why people who want to stay "in touch" are drawn to the meetings such as IEDM. With at least six sessions being ran in parallel even the most diligent attendee won't be able to listen to more than some 15% of all the talks given. So, in terms of technical contents the best source of information is a Technical Digest containing all the papers presented (which, by the way, can be acquired at the fraction of the cost of attendence at the meeting).

Still, it is not the same as the most valuable experience come from just being there.As far as technical content is concerned my [JR] first impression is that the IEDM 2011 was mostly confirming trends in semiconductor device science and engineering that are already established rather than bringing to the surface entirely new technical solutions.

I [JR] will be more specific in this regard in the follow up blogs. [So, stay tuned...]

Synopsys to Acquire Magma Design Automation

2011-12-01T00:25:00.001-08:00

I copy from Synopsys site:

MOUNTAIN VIEW, Calif., Nov. 30, 2011 /PRNewswire/ -- Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, has signed a definitive agreement to acquire Magma® Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software headquartered in San Jose, California. Bringing together complementary technology, development and support capabilities will enable the combined company to more rapidly meet customer requirements linked to chip designs at both leading-edge and mature process nodes.

Under the terms of the merger agreement, Synopsys will acquire Magma for $7.35 per Magma share in cash, resulting in a transaction value of approximately $507 million net of cash and debt acquired. The boards of directors of both companies have unanimously approved the transaction.

The closing of the merger is subject to customary conditions, including approval by the stockholders of Magma as well as U.S. regulators. In the event the merger closes as expected in the second calendar quarter of 2012, Synopsys anticipates it to be modestly accretive to non-GAAP earnings per share in its fiscal 2012. Synopsys plans to fund the acquisition with a combination of cash and debt, with the specifics to be determined at the time of close.

"The dramatic rise in complexity of today's semiconductor designs for all process nodes requires an equally dramatic increase in designer productivity. Customers are either dealing with the very complex physics of 20-nanometer design or they are squeezing the last bit of performance and cost from designs at mature, high-value nodes. To achieve success, our customers are asking for more new EDA capabilities than ever before," said Aart de Geus, chairman and CEO at Synopsys. "This acquisition will enable Synopsys to accelerate the delivery of the technology our customers need to keep the overall cost of design in check."

[mos-ak] Final Program MOS-AK/GSA Washington DC Workshop on Dec.7 2011

2011-11-20T12:10:00.001-08:00

Final Program MOS-AK/GSA Washington DC Workshop on Dec.7 2011
====================================================
http://www.mos-ak.org/washington_dc/

* Free On-line Registration Form:
http://www.mos-ak.org/washington_dc/registration.php

* Venue:
The George Washington University Marvin Center
800 21st Street, Northwest, Suite 302
Washington, DC 20052
http://gwired.gwu.edu/marvincenter

* Agenda:
http://www.mos-ak.org/washington_dc/
With panel discussion:
Compact Model Verilog-A Standardization Panel
Geoffrey J. Coram, ADI (Moderator)
Marek Mierzwinski, Tiburon Design Automation (Introduction)
Panelists
Walter R. Curtice, WRC Consulting
Carlos Galup-Montoro UFSC, Brazil
Keith Green, TI, Compact Modeling Council
Benjamin Iniguez, URV, FP7 COMON Network

Local Organizing MOS-AK/GSA Committee:
======================================
Mona Zaghloul, GWU
Can E. Korman, GWU
John Suehle, NIST

Extended MOS-AK/GSA Committee:
==============================
Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
Chelsea Boone, Director of Research GSA
* MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Geoffrey Coram, Analog Devices
Jamal Deen, U.McMaster
Roberto Tinti, Agilent EEsof Division
* MOS-AK/GSA South America:
Chair: Gilson I Wirth; UFRGS; Brazil
Prof. Carlos Galup-Montoro, UFSC; Brazil
Sergio Bampi, UFRGS, Brazil
Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
* MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Alexander Petr, XFab
Benjamin Iniguez, URV
James Victory, Sentinel-IC
* MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Sadayuki Yoshitomi, Toshiba, Japan
A.B. Bhattacharyya, JIIT, India
Xing Zhou, NTU, Singapore

[mos-ak] BSIM EKV Workshop at EPFL Lausanne on Dec. 15-16, 2011

2011-11-11T14:22:00.001-08:00

Invitation to

The Nano-Tera Workshop on the Next Generation MOSFET Compact Models
15-16 December, 2011, EPFL

The BSIM group recently proposed BSIM6 as the new MOSFET compact model
to eventually replace BSIM3, BSIM4 and PSP for next generation bulk
CMOS processes. Trying to take advantage of the charge based features
of EKV, the BSIM research team from University of California,
Berkeley, led by Prof. Chenming Hu and the EKV modeling team at EPFL,
led by Prof. Christian Enz, decided to jointly develop the new BSIM6
compact model.

The BSIM EKV partnership has been officially announced by Profs. Hu
and Enz at the last ESSDERC-ESSIRC Conference during the MOS-AK
Workshop <http://mos-ak.org/helsinki/#BSIM-EKV>. The Nano-Tera
Workshop on the Next Generation MOSFET Compact Models will convene all
the BSIM and EKV researchers as well as the experts from the industry
to give an update on the latest status of BSIM6 and EKV (and
eventually other models as well) to the modeling and designer
community.

The detailed workshop program is available at: <http://ekv.epfl.ch/
workshop>

Space and time combine to overpower the human brain

2011-10-07T04:12:00.000-07:00

Rich Goldman VP from Synopsys concluded that by the middle of this century, computing power will exceed the thinking capacity of all the humans beings on the planet.

For example, Goldman said, a 1982 Intel 80286 was 28 times more powerful than computers on the Voyagers 1 and 2, launched in 1977. Sputnik computers were capable of only 2,000 instructions per second. And a 2010 Apple iPad is 689 times more powerful than the onboard computers on the Columbia space shuttle, first launched in 1981. [read more]

[mos-ak] C4P MOS-AK/GSA Workshop in Washington DC on Dec. 7 2011

2011-10-04T14:20:00.001-07:00

C4P MOS-AK/GSA Workshop in Washington DC on Dec. 7 2011
-------------------------------------------------------
http://www.mos-ak.org/washington_dc/
-------------------------------------------------------
Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop in
Washington DC on Dec. 7 2011

The MOS-AK/GSA Workshop is HiTech forum to discuss the frontiers of
the electron devices modeling with emphasis on simulation-aware
models. Original papers presenting new developments and advances in
the compact/spice modeling and its Verilog-A standardization are
solicited. The main topics of the workshop are: (but are not limited
to):
* Compact Modeling (CM) of the electron devices
* VHDL-AMS/Verilog-A for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Transistor Level IC support
* Nanoscale CMOS devices and circuits
* Reliability and thermal management of electron devices
* Technology R&D, DFY, DFT and IC designs
* Foundry/Fabless interface strategies

The terms of participation:
-------------------------------------------------------
Authors are asked to submit a short (~200words) abstract using on-
line
submission form by OCT.30 http://www.mos-ak.org/washington_dc
Intending authors should also note the following deadlines:
* Announcement and Call for Papers - Oct 2011
* on-line abstract submission deadline - OCT.30, 2011
* Final Workshop Program - Nov. 2011
* MOS-AK/GSA Workshop - Dec. 7, 2011
-------------------------------------------------------
Further details and updates and on-line workshop registration:
http://www.mos-ak.org/washington_dc
Email contact: washington_dc@mos-ak.org
-------------------------------------------------------

Institute of Electron Technology (ITE Warsaw, PL) - IC Design

2011-10-04T05:08:00.000-07:00

IBM Seeking:

2011-10-02T14:44:00.000-07:00

For Analog/Mixed Signal Predictive Device, Process Simulation (TCAD) Engineer
[check: http://bit.ly/ny9DkU] #jobs #vermont

Nonvolatile Memory Standard CMOS Process

2011-09-30T02:46:00.000-07:00

A Japanese research group developed a technology to realize a nonvolatile memory by using only a standard CMOS process for logic chips. [more]

8th International Conference on Devices, Circuits and Systems (ICCDCS)

2011-09-23T13:22:00.000-07:00

ICCDCS is an IEEE-EDS technically sponsored international conference biannually held since its first edition (Caracas, 1995) at different locations within the Caribbean basin. Over time this conference has acquired a prestigious position as the outstanding international IEEE conference dealing with Electron Devices and Circuits and Systems which takes place within the Latin American Region.

Its main objective is to serve as a significant meeting point and technical forum to initiate, renew and maintain direct personal relations aimed at sharing relevant technical know-how among Latin American and rest-of-the-world professionals involved in the disciplines that it covers. Industry, Universities and R&D Institutions are invited to participate. English is the official working language of the Conference, although Spanish and Portuguese are also freely used in informal communications.

Prospective authors are invited to submit contributions for oral presentations to be reviewed by the Technical Program Committee. They should deal with new results, relevant ideas or innovations that advance the state-of-the-art in the areas of the Technical Program. Topics may span from basic theory to industrial applications, research, development, design, technology and applications of electron devices, analysis, design, and practical implementation of circuits, and their application to power electronics, telecommunications and instrumentation.

Location:

The ICCDCS'12 will be held on Playa del Carmen, México, from March 14 through March 17, 2012

You can download the pdf version of the Call for Papers here.

[Internship] Modeling of GaN Power Transistors for IC Design

2011-09-23T01:36:00.000-07:00

Internship framework: At the heart of the MINATEC innovation campus, Leti institute is one of the most important R&D laboratories in Europe in the field of microelectronics and nanotechnologies. Within the Alternative Energies and Atomic Energy Commission, CEA-Leti is developing GaN-based technologies and power devices for energy conversion in different industrial fields (energy management, automotive electronics, electric car). In order to design and simulate integrated circuits, it is mandatory to develop electro-thermal models of power transistors.

Work description: The aim of the internship is to develop a specific model for GaN-based high electron mobility transistors (HEMTs). This wide bandgap semiconductor is one of the most promising for power electronics and is currently the subject of extensive research. This internship will take place in the Simulation and Modeling laboratory (LSM) of the Silicon Components Division (DCOS).

This internship is divided into four parts:

Understanding of physical phenomena (electrical, thermal) in power HEMT transistors and analysis of existing models
TCAD numerical simulations of devices.
Compact modeling of transistors starting from previous studies on silicon carbide (SiC) transistors.
Depending on availability, static and pulsed measurements on GaN transistors and extraction of model parameters.

Host Institution
Direction/Département/Service/Laboratoire CEA-LETI – DRT/DCOS/SCME/LSM
Postal address
CEA/GRENOBLE, MINATEC Campus,
17 rue des Martyrs 38054 Grenoble CEDEX 9
France

Technical Supervisor
Patrick MARTIN
Phone: 04 38 78 67 05

SPICE3: Prehistory, The Dark Age and Renaissance

2011-09-22T02:46:00.000-07:00

[more: Paolo Nenzi, "ngSpice - a GNU standardization perspective" at MOS-AK/Helsinki]

Digging into Technology's Past

2011-09-19T15:38:00.000-07:00

This detailed line drawing of the MOS Technology 6502 microprocessor is a physical description of all the connections between the various circuits on the chip. (Courtesy Greg James, Visual 6502, more in archaeology by Nikhil Swaminathan)

FAST-SPICE BETA TESTERS WANTED

2011-09-13T08:38:00.000-07:00

All participants in the beta-testing program will receive the Symica Fast-SPICE product SymSpice Turbo as a free addition to the Symica tool suite. If you'd like to be a beta tester for the SymSpice Turbo, please send a request to support@symica.com. [more at: http://www.symica.com/news/fast-spice-beta-testers-wanted]

Ballot of May 28, 1948

2011-09-09T14:20:00.000-07:00

more at flickr by johngineer

“The Ugly Duckling,” New Fairy Tales

2011-09-01T15:21:00.000-07:00

"The developments of UF process-based “compact” MOSFET models have been reviewed, and exemplary new physical insights on SOI devices attained with the models have been overviewed. Indeed, the UF models have been, and are effective research/education tools. The “ugly duckling” has prevailed, just like in the fairy tale (illustrated in Fig. 10) [19]!" J. G. Fossum

[19] H. C. Anderson, “The Ugly Duckling,” New Fairy Tales. C. A. Reitzel, Copenhagen, Denmark, Nov. 1843.

J. Fossum, “UF ‘ Compact ’ Models : A Historical Perspective,” Nanotech, vol. 2, pp. 714 - 719, 2011.

Operation and Modeling of the MOS Transistor

2011-08-31T00:58:00.000-07:00

Yannis Tsividis and Colin McAndrew

New to this edition:

Energy bands and the energy barrier viewpoint are integrated into the discussion in a smooth, simple manner
Expanded discussion of small-dimension effects, including velocity saturation, drain-induced barrier lowering, ballistic operation, polysilicon depletion, quantum effects, gate tunneling current, and gate-induced drain leakage
Expanded discussion of small-signal modeling, including gate and substrate current modeling and flicker noise
New chapter on substrate nonuniformity and structural effects, discussing transversal and lateral (halo) doping nonuniformity, stress and well proximity effects, and statistical variability
A completely re-written chapter on modeling for circuit simulation, covering the considerations and pitfalls in the development of models for computer-aided design
Extensively updated bibliography
An accompanying website includes additional details not covered in the text, as well as model computer code

ISBN-10: 0195170156 | ISBN-13: 978-0195170153 | Edition: 3

[mos-ak] Final Program MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Helsinki on Sept.16 2011

2011-07-24T13:36:00.001-07:00

Please visit the MOS-AK/GSA Helsinki web site with the final workshop
program:
http://www.mos-ak.org/helsinki/

* Free On-line Registration Form:
http://essderc2011.org/registration_form.php

* Venue: Finlandia Hall in Helsinki, Finland
http://www.essderc2011.org/venue.php

* Agenda: Sept. 16, 2011: 8:30 - 16:30
http://www.mos-ak.org/helsinki/
With panel discussion: "40th Anniversary of SPICE"
(panelists alphabetic list)
Narain D. Arora, Siltera, USA
Christian Enz, EPFL, CH
Chenming Hu, UC Berkeley, USA
Willy Sansen, ESAT-MICAS, B (moderator)
Andrei Vladimirescu, BWRC, UC Berkeley, USA
Andreas Wild, ENIAC - JU, EU

Post Doctoral Researcher / Research Engineer Position in Compact Modeling

2011-07-18T11:25:00.000-07:00

The BSIM Group of Electrical Engineering Department at the University of California Berkeley is seeking to hire a bright candidate interested in compact model development/maintenance to join as a post doctoral researcher or research engineer. We are looking for a candidate with PhD (for post doctoral researcher) or Masters (for Research Engineer) degree in EE/Physics preferably for long term (4–5 years). The responsibilities include but not limited to

Research and development of new BSIM compact models
Maintenance and support of BSIM MOSFET compact models (BSIM4, BSIMSOI and BSIM-MG)
Interface with industry to understand requirements and issues with BSIM models and rectify them
C & Verilog-A coding and testing/debugging of models

Required skills

Excellent semiconductor device physics and process technology knowledge
Experience in computer programming (C and Verilog-A)
Knowledge of basic analog and digital circuit operation

BSIM Group encourages its members to represent it actively at conferences, workshops, and meetings. Interested applicants should submit their CV to bsimgroup@gmail.com

For more information, please visit:
BSIM Group and Device Group

Arrays of indefinitely long uniform nanowires and nanotubes

2011-06-29T05:28:00.000-07:00

Nature Materials | Letter

Arrays of indefinitely long uniform nanowires and nanotubes

Nature Materials 10, 494–501 (2011)

doi:10.1038/nmat3038

http://www.nature.com/nmat/journal/v10/n7/full/nmat3038.html

It's frankly nice.... see one of their pictures (hope they don't get too upset!):

SISPAD 2011 Companion Workshops

2011-06-23T01:22:00.000-07:00

September 7, 2011; Hotel Hankyu Expo Park, Osaka, Japan

Compact Modeling

Organizer: Sadayuki Yoshitomi, Toshiba Corporation

Power Devices

Organizer: Ichiro Omura, Kyusyu Institute of Technology

[link]

SuVolta creates new transistor option for 20 nm

2011-06-23T00:11:00.000-07:00

SuVolta creates new transistor option for 20 nm: "SuVolta, a startup process IP company with deep roots indevice design and m..."

Job offers at RF Micro Devices (RFMD)

2011-06-22T03:54:00.000-07:00

I've seen that there are three job offers for Compact Modeling engineers at RFMD:

Tracking Code Job Title Location Date Posted

12134	Senior Modeling Engineer	Greensboro, NC, US	6/7/2011

12134

Senior Modeling Engineer

Greensboro, NC, US

6/7/2011

12117	Sr. TCAD Modeling Engineer	Greensboro, NC, US	5/26/2011

12117

Sr. TCAD Modeling Engineer

Greensboro, NC, US

5/26/2011

12116	Sr. Modeling Engineer	Greensboro, NC, US	5/24/2011

12116

Sr. Modeling Engineer

Greensboro, NC, US

5/24/2011

Note that this is only a re-diffusion of some information we've got, and that we're not related to them in any way!

Get your own version of Myfab LIMS

2011-06-17T01:41:00.001-07:00

Myfab is the Swedish national research infrastructrue for micro and nano fabrication. Use the best cleanroom facilities in Sweden through our laboratory network and bring new scope and opportunity to your research and technical development. [read more]

IMEC benchmarks FinFET superiority

2011-06-17T00:47:00.000-07:00

IMEC benchmarks FinFET superiority:

By Peter Clarke, EE Times -- EDN, June 16, 2011

LONDON - The IMEC research institute has compared one planar and two FinFET technologies to see how they perform against scaling and process variability.

The benchmark circuits were six-transistor SRAM cells and SRAM arrays and IMEC has concluded that the FinFET outperforms planar CMOS in variability-aware and technology-aware comparison of SRAM product yield.

Both FinFET on bulk and FinFET on silicon-on-insulaor (SOIFF) technologies come out superior to the planar technology for medium- to large-sized SRAM arrays resulting in higher yields, IMEC said, although it did not disclose the process geometry at which the tests were done. It is likely to have been at around 28 to 22 nm.

As the dimensions of devices scale down, the variations in the electrical parameters of CMOS transistors steadily increase. This is due to random fluctuations in the density of the dopants in the channel, source, and drain. So, two closely placed transistors that are supposedly identical can show a widely different behavior. This makes the design of SRAM memory cells less predictable and controllable for every new technology node.

Because of this scaling 6T planar SRAMs below 22 nm remains challenging, IMEC said. FinFET devices show a lower leakage and variability and it is possible to design more compact cells.

Both FinFET technologies come out as superior to planar for SRAM arrays of greater than 128 kbytes. They are less sensitive to mismatches, thus allowing a more aggressive scaling of the power supply and a lower VCC than planar arrays. For undoped silicon-on-insulator FinFETs (SOIFF), the power supply can be lowered by an additional 200-mV compared to planar. As a sample result: undoped SOIFF FinFET allow for a 95% yield at 0.7-V in 32-Mbit SRAM arrays, moving to Gbit arrays for higher voltages.

A new birth in the IEEE journals world...

2011-06-15T08:13:00.000-07:00

Let's welcome them!

They are starting with some interesting papers on low-power and analog design with nanometer-scale variations.... Let's hope they go on...

IEEE Journal of Emerging and Selected Topics in Circuits and Systems (JETCAS)

We are honored to welcome readers and authors to the inaugural issue of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS for short), which is sponsored by the IEEE Circuits and Systems Society (CAS-S.)

The journal, which is freely accessible on-line to all CAS-S members, aims to build a platform for the broad and timely dissemination of key innovative results and findings in rapidly-growing and/or emerging topic areas within the scope of the IEEE Circuits and Systems Society. Such potentially interdisciplinary emerging topics will be selected as long as, first, they are clearly situated at the forefront of current scientific and technological developments and, second, they are expected to grow over time in scientific and professional importance and, therefore, in the number of active practitioners. From this point of view, JETCAS is expected to create new communities interested in the long-term development of the most promising subjects presented in the journal. The editorial strategy followed by JETCAS will be the publication of Special Issues on the selected topics. These issues will include research contributions from leading experts and presentations geared towards a wide audience of scientists and pra

MASSOUD PEDRAM, Editor-in-Chief (EiC)

MANUEL DELGADO-RESTITUTO, Deputy EiC

ENRICO MACII, 2010-2011 VP Publications, IEEE CAS-S

GIANLUCA SETTI, 2010 President, IEEE CAS-S  


Volume 1, Issue 1 - Inaugural Edition
http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=5503868

Pedram, M.;  Delgado-Restituto, M.;  Macii, E.;  Setti, G., Inaugural Editorial
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5765455

-----------------------------------------------------------------------------------------------------
Variation-Aware Design for Nanoscale VLSI Circuits and Systems
The focus of this issue is on the challenges faced in designing digital and analog circuits in nanoscale technologies, where variations due to process, environmental, and aging variations are substantial.  The root causes of these effects can generally be traced to scaling: with the drive towards even greater miniaturization, these problems become even more acute and it is imperative that they be addressed.  The solutions involve the invention of improved design techniques, better design automation, and closer interactions between the phenomenological root causes and the designer.  The six papers in this issue attempt to provide a view of the landscape, reflecting the current state of the art and future directions.

Sapatnekar, S. S., Guest Editorial
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5762378

------------------------------------------------------------------------------------------------------------------
Sapatnekar, S. S., Overcoming Variations in Nanometer-Scale Technologies
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5762377
Nanometer-scale circuits are fundamentally different from those built in their predecessor technologies in that they are subject to a wide range of new effects that induce on-chip variations. These include effects associated with printing finer geometry features, increased atomic-scale effects, and increased on-chip power densities, and are manifested as variations in process and environmental parameters and as circuit aging effects. The impact of such variations on key circuit performance metrics is quite significant, resulting in parametric variations in the timing and power, and potentially catastrophic failure due to reliability and aging effects. Such problems have led to a revolution in the way that chips are designed in the presence of such uncertainties, both in terms of performance analysis and optimization. This paper presents an overview of the root causes of these variations and approaches for overcoming their effects.
-----------------------------------------------------------------------------------------------------------------
Karakonstantis, G.;  Chatterjee, A.;  Roy, K., Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5766061
The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs (logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power b
-----------------------------------------------------------------------------------------------------------------
Mitra, S.;  Brelsford, K.;  Kim, Y. M.;  Lee, H.-H. K.;  Li, Y., Robust System Design to Overcome CMOS Reliability Challenges
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751208
Today's mainstream electronic systems typically assume that transistors and interconnects operate correctly over their useful lifetime. With enormous complexity and significantly increased vulnerability to failures compared to the past, future system designs cannot rely on such assumptions. For coming generations of silicon technologies, several causes of hardware reliability failures, largely benign in the past, are becoming significant at the system level. Robust system design is essential to ensure that future systems perform correctly despite rising complexity and increasing disturbances. This paper describes three techniques that can enable a sea change in robust system design through cost-effective tolerance and prediction of failures in hardware during system operation: 1) efficient soft error resilience; 2) circuit failure prediction; and 3) effective on-line self-test and diagnostics. The need for global optimization across multiple abstraction layers is also demonstrated.
-----------------------------------------------------------------------------------------------------------------
Seok, M.;  Chen, G.;  Hanson, S.;  Wieckowski, M.;  Blaauw, D.;  Sylvester, D., CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5762379
Near threshold computing has recently gained significant interest due to its potential to address the prohibitive increase of power consumption in a wide spectrum of modern VLSI circuits. This tutorial paper starts by reviewing the benefits and challenges of near threshold computing. We focus on the challenge of variability and discuss circuit and architecture solutions tailored to three different circuit fabrics: logic, memory, and clock distribution. Soft-edge clocking, body-biasing, mismatch-tolerant memories, asynchronous operation and low-skew clock networks are presented to mitigate variability in the near threshold ${V} _{rm DD}$ regime.
-----------------------------------------------------------------------------------------------------------------
Maricau, E.;  Gielen, G., Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5762376
Integrated analog circuit design in nanometer CMOS technologies brings forth new and significant reliability challenges. Ever-increasing process variability effects and transistor wear-out phenomena such as BTI, hot carrier degradation and dielectric breakdown force designers to use large design margins and to increase the uncertainty on the circuit lifetime. To help designers to tackle these problems at design time (i.e., Design For Reliability, or DFR), accurate transistor aging models, efficient circuit reliability analysis methods and novel design techniques are needed. The paper overviews the current state of the art in DFR for analog circuits. The most important unreliability effects in nanometer CMOS technologies are reviewed and transistor aging models, intended for accurate circuit simulation, are described. Also, efficient methods for circuit reliability simulation and analysis are discussed. These methods can help designers to analyze their circuits and to identify weak spots. Finally, cost-effect
-----------------------------------------------------------------------------------------------------------------
Zhang, X.;  Mukadam, M. Y.;  Mukhopadhyay, I.;  Apsel, A. B., Process Compensation Loops for High Speed Ring Oscillators in Sub-Micron CMOS
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5756255
In this paper, we present two implementations of a closed-loop process compensation scheme for high speed ring oscillators-the comparator based and the switched capacitor based loops. We provide detailed discussion of the frequency accuracy, loop stability, and implementation cost for each design. More than 150 test chips from multiple wafer-runs in a 90 nm CMOS process verify that frequency accuracy of better than 2.6% can be achieved with the application of the proposed compensation loop. Moreover, by leveraging a low variation addition-based current source, we have demonstrated a fully-integrated 2.15 GHz ring oscillator with less than 4.6% frequency variation without external references or post fabrication calibration, which is 3.8 $times$ improvement in frequency accuracy over the baseline case. The same compensation scheme can also alleviate frequency drift caused by temperature.

JETCAS is published quarterly and solicits, with particular emphasis on emerging areas, special issues on topics that cover the entire scope of the IEEE Circuits and Systems (CAS) Society, namely the theory, analysis, modeling, design, automation, and implementation of electronic circuits and systems, spanning theoretical foundations, applications, and architectures for signal and information processing.

First Graphene Integrated Circuit

2011-06-12T17:03:00.001-07:00

IBM researchers have built the first IC based on a graphene transistor. It is another step toward overcoming the limits of silicon and a potential path to flexible electronics [read more at spectrum.ieee.org]

Alternative semiconductor fabrication methods enable inexpensive, conformable consumer devices - Solid State Technology

2011-06-09T23:47:00.000-07:00

Alternative semiconductor fabrication methods enable inexpensive, conformable consumer devices - Solid State Technology

Emerging technology and a developing infrastructure for printed electronics is enabling circuitry that is flexible, conformable, and inexpensive to mass-produce. FlexTech Alliance has identified, funded, and directed advanced development in the flexible and printed electronics infrastructure, paving the way for the practical manufacture of a variety of low-cost applications such as electronic packaging, ID tags, and wide-area lighting panels.

Printed electronics include a set of consumer markets where printed logic and memory will be required. The size and cost of fully printed systems is set to challenge silicon-based technologies in ultra-high-volume distributed applications. To address this issue, Norwegian firm ThinFilm Electronics produces rewritable memory tags manufactured using full roll-to-roll (R2R) printing. Printed non-volatile RAM (NVRAM), when combined with printed transistor elements, serves as the basis of a new generation of cheap, disposable, and highly ubiquitous electronic devices. The company is working with major toy and game companies and has established high-volume manufacturing to deliver millions of tags per month.

In other commercial development, a new method for fabricating printed semiconductors, developed by NthDegree Technologies, allows a standard high-speed printing press to print conductive ink on to paper, plastic, or other substrate materials. Printed semiconductors made with these inks reduce the cost of producing semiconductor-based devices while creating innovative conformable products. Wide-area lighting is currently being produced with this technology by means of a light-emitting diode (LED) "ink". This LED ink is being used to print area lighting that is converted into a flat panel to replace fluorescent tube fixtures.

These latest developments in printed electronics materials, tools and processes, including LED lighting and printed memory, will be discussed and demonstrated at the Extreme Electronics TechXpot session "Printed electronics: Beyond R&D to real-deal technologies," presented by the FlexTech Alliance at SEMICON West, July 14, 2011. For more information about FlexTech Alliance visit www.flextech.org.

Freescale's Su calls for improved EDA tools

2011-06-09T23:37:00.000-07:00

Freescale's Su calls for improved EDA tools:

As more embedded devices are being connected to the "Internet of things" the design methodologies used in IC designs need to change accordingly for faster chip turnarounds.

Lisa Su, VP and general manager of Freescale"Some 7 billion devices will be connected to the Internet in this era from 2006 to 2020," said Lisa Su, vice president and general manager of Freescale Semiconductor Inc's networking and multimedia group. "And mobile traffic is doubling every year through 2015."

Su delivered the Tuesday (June 7) keynote here at the Design Automation Conference, whose organizers have placed embedded systems and software squarely in the apex of DAC with dedicated exhibit areas on the show floor.

While only 15 exhibitors specifically identified themselves as embedded hardware/software providers out of a total of 200, the technical program was loaded with embedded presentations and Su's keynote was clearly aimed at showing that at least Freescale understands that it is operating in a new space for them, the embedded world.

"The embedded era is defined by standards-based hardware and software, is open source, and aimed numerous markets, including health, safety, energy, transportation, communications, entertainment, automation, and, of course, cloud computing," said Su.

Su quoted statistics that the monthly mobile traffic will increase tenfold from today's 0.6 exabytes to 6.3 exabytes by 2015. "The resultant heterogeneous networks, together with the increasing needs of the â€˜connected' car, offer many opportunities to semiconductor companies like us," said Su.

The many-core paradigm of the expected SOC technology transition poses a few challenges, according to Su.

Among these are scalability as the number of cores per processor generation will double. Also there will be system tradeoffs to consider between cores versus using hardware acceleration, as well cluster optimization among cores, caches, local vs. global resource sharing. And an increasing amount of high-speed mixed-signal I/O will place strain on expected quality of service metrics.

read more...

Postdoc Position in Thin Films (Thun, CH)

2011-06-08T01:29:00.000-07:00

Empa is the interdisciplinary research and services institution for material sciences and technology development of the ETH Domain. Laboratory for Mechanics of Materials and Nanostructures at Empa's location in Thun, CH, is offering an Academia / Industry Postdoc Position in Thin Films

Submit your application online and upload all documents through this webpage by June 30, 2011:
http://internet1.refline.ch/673276/0190/++publications++/1/index.html

Additional information can be obtained from the EMPA website and by contacting Dr. Johann Michler.

IEDM'2011 Abstract Submission Site is Now Open (Deadline: June 24, 2011)

2011-06-07T23:54:00.001-07:00

IEDM Abstract Submission Site is Now Open - Abstract Submission
Deadline:   June 24, 2011

2011 IEEE International Electron Devices Meeting
The Annual Technical Meeting of the Electron Devices Society will be held at the
Washington Hilton, Washington, DC USA  - December 5-7, 2011

To view the IEDM Call for Papers and instructions for submitting an abstract to
the conference, visit:      http://www.ieee-iedm.org

IEEE International Electron Devices Meeting (IEDM) is the world’s pre-eminent
forum for reporting technological breakthroughs in the areas of semiconductor
and electronic device technology, design, manufacturing, physics, and modeling. 
IEDM is the flagship conference for nanometer-scale CMOS transistor technology,
advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale
devices and phenomenology, optoelectronics, devices for power and energy
harvesting, high-speed devices, as well as process technology and device
modeling and simulation.  

Starting this year (2011) there is an increased emphasis on circuit and device
interaction.  With ever increasing transistor count, nanometer design rules and
layout restrictions, circuit-device interaction is becoming critical to
providing viable technology solutions. This new emphasis includes
technology/circuit co-optimization, power/performance/area analyses, design for
manufacturing and process control, as well as CMOS platform technology and
scaling.

INCREASED PARTICIPATION IN THE FOLLOWING AREAS IS SOUGHT: 
 * Circuit-device interaction 
 * Energy harvesting
 * Biomedical devices
 * Power devices

Information about IEDM can be found at: http://www.ieee-iedm.org 
Twitter: http://twitter.com/ieee_iedm 
Facebook: http://www.facebook.com/pages/IEDM/131119756449 

MEETING HIGHLIGHTS 
 * New subcommittees (Circuit-Device Interaction and Nano Device Technology)
 * New for 2011:  90 Minute Tutorial Sessions on Emerging Topics, Saturday
afternoon, December 3
 * Three plenary presentations by prominent experts 
 * Invited papers on all aspects of advanced devices and technologies.
 * An Emerging Technology session. 
 * Two evening Panel discussions.
 * Presentation of IEEE/EDS awards. 
 * IEDM Luncheon presentation will be held on Tuesday, December 6.
 * Two short courses will be held on Sunday, December 4.

Further Information - All questions or inquiries for further information
regarding this meeting should be directed to the Conference Office at:

19803 Laurel Valley Place
Montgomery Village, MD 20886 USA
Tel: 301-527-0900, ext. 2
Email: iedm@his.com 
Local European Contact 

Stefan De Gendt, IMEC, Belgium
Local Asian Contact 
Norikatsu Takaura, LEAP, Japan
2011 Conference Chair 
Kazunari Ishimaru, Toshiba, Japan
Technical Program Chair 
Veena Misra, North Carolina State University, USA

If you know of any colleagues who may have a paper to contribute and have not
received this notice, please bring it to their attention.

Course on Statistical CMOS Variability and Reliability, San Jose CA, June 13th and 14th

2011-06-03T00:43:00.000-07:00

Professor Asen Asenov, CEO of Gold Standard Simulations, will be delivering a comprehensive course (see the flyer) on variability and reliability issues and their impact on modern CMOS devices and design.

The course topics include, Variability classification,Sources of statistical variability, Simulation of statistical variability, Variability trends in conventional and novel MOSFETs, Random telegraph noise statistics, Statistical aspects of reliability, Statistical compact model strategies and Statistical circuit simulation. At this event there will also be a special lecture on Variability in FinFET devices.

For more information please visit: http://www.goldstandardsimulations.com/courses/ or get in touch with them at courses(at)goldstandardsimulations.com.

Papers in Solid-State Electronics Volume 62, Issue 1, (August 2011)

2011-06-02T06:07:00.000-07:00

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates Original Research Article

Pages 31-39
Darsen D. Lu, Mohan V. Dunga, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu

Research highlights

► A computationally efficient approximation for surface potential in FDSOI MOSFETs is developed. ► I–V and C–V models for FDSOI MOSFETs are derived without making the charge sheet approximation. ► The core model and non-ideal effect expressions are implemented in Verilog-A language. ► The model is symmetric with respect to V_ds = 0 and continuous in all regions of operation.

An effective thermal circuit model for electro-thermal simulation of SOI analog circuits Original Research Article

Pages 48-61
Ming-C. Cheng, Kun Zhang

Highlights

► A thermal circuit model is developed for SOI analog circuits. ► The model integrates a device thermal circuit with interconnect thermal networks. ► The device thermal circuit accounts for non-isothermal effects in SOI devices. ► Thermal networks for cross-coupled and parallel coupled wires are developed. ► The model is coupled with BSIMSOI for electro-thermal simulation of SOI circuits.

MOSFET modeling for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures: Case of an analog/digital 0.18 μm CMOS process Original Research Article

Pages 115-122
P. Martin, A.S. Royet, F. Guellec, G. Ghibaudo

Research highlights

► Specific physical effects are observed in a cooled (77–200 K) 0.18 μm CMOS process. ► These effects are described and modeled for design of cryogenic IR CMOS imagers. ► Data on low frequency noise and transistor matching in MOSFET are also presented.

Physics-based compact model for ultra-scaled FinFETs Original Research Article

Pages 165-173
Ashkhen Yesayan, Fabien Prégaldiny, Nicolas Chevillon, Christophe Lallement, Jean-Michel Sallese

Highlights

► We propose a physical and explicit compact model for lightly doped FinFETs. ► This design-oriented model is valid for a large range of silicon Fin widths/lengths. ► It describes well the drain current, small signal parameters and capacitances. ► It takes into account all short-channel effects and quantum mechanical effects. ► This compact model needs a very few number of electrical parameters (4).

Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s Original Research Article

Pages 174-184
Krishna Meel, R. Gopal, Deepak Bhatnagar

Highlights

► New 3-D front (back) gate threshold voltage models of FD-SOI MOSFETs are reported. ► Models solve 3-D Poisson’s equation using Green’s function as a tool. ► 3-D threshold voltage models include side wall, source/drain and back gate effects. ► Front and back gate charge coupling is incorporated in both the threshold voltages. ► Compact models of threshold voltages are amenable to circuit CAD tool.

Mobility analysis of surface roughness scattering in FinFET devices Original Research Article

Pages 195-201
Jae Woo Lee, Doyoung Jang, Mireille Mouis, Gyu Tae Kim, Thomas Chiarella, Thomas Hoffmann, Gérard Ghibaudo

Highlights

► Mobility analysis of the surface roughness scattering along the different interfaces of FinFET devices. ► The sidewall and top surface drain current components were estimated from the total drain currents of different fin width conditions. ► The contribution of the surface roughness scattering was analysed and that on sidewalls was about three times stronger than on top surface for n-channel FinFETs.

[mos-ak] C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Helsinki on Sept.16 2011

2011-06-01T12:02:00.000-07:00

C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Helsinki on Sept.16 2011
http://www.mos-ak.org/helsinki/

Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop in
Helsinki on Sept.16 2011 with special panel: 40th Anniversary of SPICE
(panelists tentative alphabetic list):
* Narain D. Arora, Siltera, USA
* Christian Enz, CSEM, CH
* Andrei Vladimirescu, EECS, Berkeley
* Andreas Wild, ENIAC - JU, EU
and MOS-AK/GSA Transistor Level IC Design Challenge Opening

The terms of participation:
Authors are asked to submit a short (~200words) abstract using on-line
submission form by JUNE 30 http://www.mos-ak.org/helsinki/abstracts.php

Intending authors should also note the following deadlines:
* Announcement and Call for Papers - May 2011
* on-line abstract submission deadline - June 30, 2011
* Final Workshop Program - August 2011
* MOS-AK/GSA Workshop - Sept. 16, 2011

On-line workshop registration: http://www.essderc2011.org/registration.php
Further details and updates: http://www.mos-ak.org/helsinki
Email contact: helsinki@mos-ak.org

Papers for curious people... (may 25th 2011)

2011-05-25T01:16:00.000-07:00

CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability

Stanzione, S. Puntin, D. Iannaccone, G.
Page(s): 1456 - 1463
Digital Object Identifier : 10.1109/JSSC.2011.2120650

AbstractPlus | Full Text: PDF (1209KB)

This paper presents an extreme-low-power mixed-signal CMOS integrated circuit for product identification and anti-counterfeiting, which implements a physical unclonable function operating with a challenge-response scheme. We devise a series of circuits and algorithmic solutions based on the use of a process monitor and on the prediction of the erratic response bits which allow to suppress the effects of temperature, voltage supply and process variations in order to obtain a robust and reliable b... Read More »

A Supply-Rail-Coupled eTextiles Transceiver for Body-Area Networks

Mercier, P. P. Chandrakasan, A. P.
Page(s): 1284 - 1295
Digital Object Identifier : 10.1109/JSSC.2011.2120690

AbstractPlus | Full Text: PDF (1915KB)

This paper presents a transceiver that communicates over electronic textiles as an alternative, energy-efficient communication medium for body-area network (BAN) applications. The proposed eTextiles network architecture consists of a two-wire conductive yarn medium, body-worn nodes, and a basestation used for data collection and medium-access control. Fabricated in 0.18 $mu$m CMOS technology, the eTextiles transceiver employs supp... Read More »

Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness

Ye, Y. Liu, F. Chen, M. Nassif, S. Cao, Y.
Page(s): 987 - 996
Digital Object Identifier : 10.1109/TVLSI.2010.2043694

Abstract | Full Text: PDF (1332KB)

The threshold voltage $({V}_{rm th})$ of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations which are too expensive in computation for statistical design. In this work, we develop an efficient SPICE simulation method and statistical variation model that accurately predict threshold variation as a function of dopant ... Read More »

On Functional Broadside Tests With Functional Propagation Conditions

Pomeranz, I. Reddy, S. M.
Page(s): 1094 - 1098
Digital Object Identifier : 10.1109/TVLSI.2010.2043695

AbstractPlus | Full Text: PDF (197KB)

Functional broadside tests were defined as broadside tests where the scan-in state is a reachable state. This ensures that during the functional capture cycles of the test, the circuit visits states that it can also visit during functional operation. As a result, it avoids overtesting that may occur with unreachable states. However, the scan-out operation at the end of a functional broadside test allows the observation of any fault effects that reached the state variables at the end of the secon... Read More »

Broadside and Functional Broadside Tests for Partial-Scan Circuits

Pomeranz, I. Reddy, S. M.
Page(s): 1104 - 1108
Digital Object Identifier : 10.1109/TVLSI.2010.2044049

AbstractPlus | Full Text: PDF (176KB)

Functional broadside tests were defined to address overtesting that may occur due to the detection of delay faults under nonfunctional operation conditions. Such conditions are made possible by scanning in unreachable states. Functional broadside tests were defined and studied in the context of full-scan circuits. In this work, we study the definition of broadside and functional broadside tests in partial-scan circuits. A unique property we show is that if the unscanned state variables are obser... Read More »

Papers in IEEE TED, vol 58, issue 6 (june 2011)

2011-05-25T01:10:00.000-07:00

An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET

Jandhyala, S. Mahapatra, S.
Page(s): 1663 - 1671
Digital Object Identifier : 10.1109/TED.2011.2131654

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton–Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in ... Read More »

Statistical Model of Line-Edge and Line-Width Roughness for Device Variability Analysis

Hiraiwa, A. Nishida, A. Mogami, T.
Page(s): 1672 - 1680
Digital Object Identifier : 10.1109/TED.2011.2131144

The authors propose a model of line-edge and line-width roughness (LER and LWR) of actual device patterns, which received some smoothing steps, for accurate estimation of device variability. The model assumes that LER/LWR has originally an exponential autocorrelation function (ACF) and is smoothed using another exponential function. The power spectrum of this ACF almost completely fits the experimental one of polycrystalline silicon lines, which were formed using plasma etching. The authors inve... Read More »

A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET

Bazigos, A. Krummenacher, F. Sallese, J.-M. Bucher, M. Seebacher, E. Posch, W. Moln??r, K. Tang, M.
Page(s): 1710 - 1721
Digital Object Identifier : 10.1109/TED.2011.2119487

This paper presents a novel physics-based analytical compact model for the drift region of a high-voltage metal–oxide–semiconductor field-effect transistor (HV-MOSFET). According to this model, the drift region is considered as a simple 1-D problem, just as that of a low-voltage inner MOS transistor. It exploits the charge-sheet approximation and performs linearization between the charge in the drift region and the surface potential. The drift region model combined with the standar... Read More »

Papers in IEEE EDL, vol 32, issue 6 (may 2011)

2011-05-25T01:07:00.000-07:00

Modeling of Current-Return-Path Effect on Single-Ended Inductor in Millimeter-Wave Regime

Wang, H. Zhang, L. Yang, D. Zeng, D. Wang, Y. Yu, Z.
Page(s): 737 - 739
Digital Object Identifier : 10.1109/LED.2011.2136312

The effect of current return path (CRP) on the accurate modeling of single-ended inductors in the millimeter-wave regime has been investigated. A series of spiral inductors with different sizes, shapes, and CRP positions was fabricated in a 0.18-$muhbox{m}$ RF-CMOS process and measured up to 50 GHz. An analytical appended model for CRP is developed to characterize the effect, and its equivalent circuit is validated by measurement ... Read More »

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

Duarte, J. P. Choi, S.-J. Moon, D.-I. Choi, Y.-K.
Page(s): 704 - 706
Digital Object Identifier : 10.1109/LED.2011.2127441

A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk curre... Read More »

Modeling and Separate Extraction of Gate-Bias- and Channel-Length-Dependent Intrinsic and Extrinsic Source–Drain Resistances in MOSFETs

Bae, H. Jang, J. Shin, J. S. Yun, D. Lee, J. Kim, T. W. Kim, D. H. Kim, D. M.
Page(s): 722 - 724
Digital Object Identifier : 10.1109/LED.2011.2131116

A new technique for a separate extraction of the current-path-dependent resistance $(R_{{rm SD}0})$ from the contact-dependent source and drain resistances $(R_{rm Se} hbox{and} R_{rm De})$ is reported for a single MOSFET. We also report a technique for a separation of $V_{rm GS}$ -dependent source an... Read More »

Extraction of Separated Source and Drain Resistances in Amorphous Indium–Gallium–Zinc Oxide TFTs Through – Characterization

Bae, H. Kim, S. Bae, M. Shin, J. S. Kong, D. Jung, H. Jang, J. Lee, J. Kim, D. H. Kim, D. M.
Page(s): 761 - 763
Digital Object Identifier : 10.1109/LED.2011.2127438

Considering asymmetry caused by layout, process, and device degradation, separate extraction of the source and drain resistances, i.e., $R_{S}$ and $R_{D}$, respectively, from the total resistance $R_{rm TOT}$ is very important in the design, modeling, and characterization of amorphous indium–g... Read More »

Mechanism Analysis of Off-Leakage Current in an LDD Poly-Si TFT Using Activation Energy

Nakashima, A. Kimura, M.
Page(s): 764 - 766
Digital Object Identifier : 10.1109/LED.2011.2132112

We have analyzed the mechanism of off-leakage current in an lightly doped drain (LDD) poly-Si thin-film transistor by investigating the activation energy $E_{a}$. It is found that $E_{a}$ decreases as the gate and drain voltages increase. We have also discussed the mechanism using a device simulator. It is found that a hole channel is lightly formed in the LDD regio... Read More »

Evidence of a Novel Source of Random Telegraph Signal in CMOS Image Sensors

Goiffon, V. Magnan, P. Martin-Gonthier, P. Virmontois, C. Gaillardin, M.
Page(s): 773 - 775
Digital Object Identifier : 10.1109/LED.2011.2125940

This letter reports a new source of dark current random telegraph signal in CMOS image sensors due to meta-stable Shockley–Read–Hall generation mechanism at oxide interfaces. The role of oxide defects is discriminated thanks to the use of ionizing radiations. A dedicated RTS detection technique and several test conditions (radiation dose, temperature, integration time, photodiode bias) reveal the particularities of this novel source of RTS. Read More »

Temperature Dependence of the Threshold Voltage Shift Induced by Carrier Injection in Integrated STI-Based LDMOS Transistors

Poli, S. Reggiani, S. Denison, M. Gnani, E. Gnudi, A. Baccarani, G. Pendharkar, S. Wise, R.
Page(s): 791 - 793
Digital Object Identifier : 10.1109/LED.2011.2135835

Large threshold voltage shifts $(Delta V_{t})$ are experimentally observed in n-channel lateral DMOS transistors under high current–voltage regime. The effect is enhanced by the gate voltage as well as by the ambient temperature $(T_{A})$ . By approximating the curves with the usually adopted power-law dependence ... Read More »

RF Model and Verification of Through-Silicon Vias in Fully Integrated SiGe Power Amplifier

Liao, H.-Y. Chiou, H.-K.
Page(s): 809 - 811
Digital Object Identifier : 10.1109/LED.2011.2136313

This letter proposes an RF model of through-silicon via (TSV) considering both skin-depth and lossy substrate effects up to 20 GHz. The TSV is fabricated in 0.18-$muhbox{m}$ SiGe BiCMOS process with the dimensions of 50 $muhbox{m}$ in diameter and 100 $muhbox{m}$ in depth. The equivalent circuit model... Read More »

Channel-Length-Dependent Transport Behaviors of Graphene Field-Effect Transistors

Han, S.-J. Chen, Z. Bol, A. A. Sun, Y.
Page(s): 812 - 814
Digital Object Identifier : 10.1109/LED.2011.2131113

This letter presents a detailed study of transport in graphene field-effect transistors (GFETs) with various channel lengths, from 5 $muhbox{m}$ down to 90 nm, using transferred graphene grown by chemical vapor deposition. An electron–hole asymmetry observed in short-channel devices suggests a strong impact from graphene/metal contacts. In addition, for the first time, we observe a shift of the gate voltage at the Dirac poi... Read More »

Marie Curie PhD position in Catania, Italy

2011-05-20T08:55:00.000-07:00

Dear Colleague,

it is a pleasure to inform you that a Marie Curie Early Stage Researcher
position is available at the Institute for Microelectronics and
Microsystem of the National Research Council of Italy (IMM-CNR) in
Catania.
The position is on the topic "Physical issues at interfaces and
nanoscale in advanced SiC devices", and it is open in the framework of
the FP7 Marie Curie ITN - NetFISiC (Training NETwork on Functional
Interfaces for SiC).

You can find more information on the position in the following link:

http://ec.europa.eu/euraxess/index.cfm/jobs/jobDetails/33681023

Would you please inform all the potential applicants for this position
(graduated students in Physics, Engineering or Material Science ) about
this good opportunity.

Should you need more information, contact:

Fabrizio Roccaforte
CNR-IMM
Strada VIII n.5, Zona Industriale
I-95121 Catania
Italy
tel. +39-0955968226
fax. +39-0955968312
e-mail: fabrizio.roccaforte@imm.cnr.it

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, MAY 2011

2011-05-17T00:01:00.000-07:00

A physically based, accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal-oxide-semiconductor field-effect transistors

M. A. Karim^1,2,*,
Q. D. M. Khosru¹

Article first published online: 12 MAY 2011

DOI: 10.1002/jnm.817

Issue

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Early View (Online Version of Record published before inclusion in an issue)

Open Ph D scholarship in semiconductor device modeling

2011-05-12T12:48:00.000-07:00

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be for four years. The monthly salary will be about 1000 Euro/month. The position will start in September 2011.

The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices, in particular nanoscale MOSFETs. It will be related to several European projects in which the hosting group participates, in particular the COmpact MOdelling Netwok (COMON), that is led by the hosting group (the so-called NEPHOS group) and the SQWIRE (Silicon Quantum WIREs) project, about junctionless nanowires.

The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.

Required documents for applicants

Applicants are required to send to the address specified below the following documents (in English or Spanish):

1) a full Curriculum Vitae (as complete as possible) with passport number

2) Copy of their diploma

3) copy of their passport

4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.

Candidates are requested to send their documents by e-mail to:

Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering

Universitat Rovira i Virgili (URV)

Avinguda Països Catalans, 26
43007 Tarragona (Spain)
Email: benjamin.iniguez@gmail.com
Tel: +34977558521 Fax:+34977559610

Deadline: May 31 2011

You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@gmail.com) for more information

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat and sauron.etse.urv.es

Spice simulation, Tina-TI, LTSpice, PSpice, and more

2011-05-11T00:37:00.000-07:00

Spice simulation, Tina-TI, LTSpice, PSpice, and more: "I got a nice note from the irrepressible Mary Dunnie that Texas Instruments h..."

job offer at Mentor

2011-05-10T02:10:00.000-07:00

As today (May 10, 2011), there is an open position as pre-sales engineer at Mentor. More details here.

π Raspberry Pi Foundation

2011-05-06T15:51:00.000-07:00

The Raspberry Pi Foundation is a UK registered charity (Registration Number 1129409) which exists to promote the study of computer science and related topics, especially at school level, and to put the fun back into learning computing [read more...]

Reflections from ISSCC 2011

2011-05-06T12:37:00.000-07:00

Sotiris Bantas, VP Technology, Helic Inc., has posted his reflections from ISSCC 2011. Surly you will enjoy reading this: http://goo.gl/HB0ka

TSMC not following Intel to Finfets at 22nm - waiting till 20nm

2011-05-06T01:17:00.000-07:00

Nearly a decade ago, TSMC demo-ed a 25nm Finfet - what Intel calls a Tri-Gate - transistor [more at Mannerisms]

Celebrating engineering: EDN names 2010 Innovation Award winners

2011-05-05T15:45:00.000-07:00

Celebrating engineering: EDN names 2010 Innovation Award winners: "San Jose, CA—In aceremony here Monday evening, EDN bestowed its 2..."

Category: EDA Tools and ASIC TechnologiesThe finalists in this category—Apache Design Solutions, GateRocket Inc, GlobalFoundries, and Mentor Graphic—are recognized for innovations in design automation tools that reduce cycle time, increase manufacturability, and improve the reliability of integrated circuits. "Tonight's winner has achieved two of the most difficult feats in the EDA industry," Technical Editor Mike Demler said. "First, it has a history of developing innovative, differentiated products. This latest innovation addresses the problem of simulating electro-static discharge that has challenged designers for many years. The second distinction is to leverage that success into a proposed IPO."

Winner: Apache Design Solutions

Intel And Seagate: Silicon Transistor And Magnetic Storage Density Maintain An Impressively Steady Improvement Rate - Brian's Brain | Blog on EDN

2011-05-05T15:43:00.000-07:00

Intel And Seagate: Silicon Transistor And Magnetic Storage Density Maintain An Impressively Steady Improvement Rate - Brian's Brain Blog on EDN

Two fundamental technology breakthroughs in two days; these are the times that tech editors dream of! I’ve in the past drawn a correlation between Moore’s Law (named for Intel’s Gordon), a forecast of the pace of single-chip transistor integration increase over time first made in 1965, and the rate of capacity growth over time (said another way, cost-per-capacity) for both magnetic and semiconductor storage. Solid-state drives, of course, are direct beneficiaries of Moore’s prescience, but areal density increases in magnetic storage are at least as impressive if not more so.

[mos-ak] MOS-AK/GSA Paris Workshop Press Release

2011-04-27T13:36:00.001-07:00

MOS-AK/GSA Modeling Working Group Holds Spring Workshop in Paris
Experts Share Insight on Compact Device Modeling with Emphasis on
Simulation-Aware Models

Press release: http://gsaglobal.org/news/article.asp?article=2011/0426

On-line publications: http://www.mos-ak.org/paris/

The MOS-AK/GSA Modeling Working Group has several upcoming events:
* special modeling session at the MIXDES Conference in Gliwice, Poland
(https://www.mixdes.org/Special_sessions.htm);
* autumn MOS-AK/GSA workshop in Helsinki, Finland;
* winter MOS-AK/GSA meeting in Washington, D.C., USA.

TSMC lays out their 20nm roadmap, no disruption from Japan.

2011-04-07T00:08:00.000-07:00

Cited from EDN: TSMC lays out their 20nm roadmap, no disruption from Japan.:

TSMC kicked off their annual Technology Symposium series in San Jose today. Founder, Chairman and CEO Morris Chang opened the proceedings by addressing concerns for how Japan’s disaster recovery will impact the foundry’s supply chain. Dr. Chang listed a number of issues that had been of concern; metal sputtering targets, CMP (chemical-mechanical polishing) slurry, raw silicon wafers, chemicals, tools and spare parts. However, he assured the audience, TSMC has been able to solve all supply problems and “everything is under control, no supply shortages will interrupt the production lines“.

TSMC does expect an impact on their customers, however, and their customer’s customers. Dr. Chang said that there will be some effect on the industry in Q2 and possibly into Q3, but the impact would be no more than two quarters. This will add to a slight softening in the world economy; including Chinese efforts to fight inflation, problems in Europe, some economic measures in U.S., with the end result being that 2011 will be less strong than TSMC had originally thought. The company is resetting their forecast from 7% growth down to 4%.

Dr. Chang then went on to describe how the semiconductor market drivers have changed; from PCs (1980-2000), to cell phones (2000 - 2010), to today’s “killer app” - mobile products, including smartphones, tablets, and any “devices you carry around“.

Moving to more technical topics, Dr. Chang predicted that the 20nm process that they have in development will provide 2X the performance over 28nm. TSMC has also begun investigation at 14nm, and “Moore’s law still has some distance to go“, according to Chang. He also noted that the company has “significant R&D” in 3D IC technology; including 2/2.5D interposers, TSV (through-silicon vias), and what the company refers to as “system-level scaling“.

Dr. Chang concluded by comparing TSMC’s capacity (2 - 12″ fabs produce up to 260,000 wafers/month), to competitors, stating that they are building capacity but they don’t have the technology, that what competitors have is not “effective capacity“. TSMC is also working on production of 450mm wafers. Pilot production is targeted for 2013-14, with an “intercept point” for production of 20nm in 2015-16.

The 20nm roadmap

Next up on the morning’s agenda was Dr. Shang-Yi Chiang, TSMC’s Sr. VP R&D, to go over TSMC’s advanced technology roadmap. Looking out to the next process node, Dr. Chiang said that the 20nm (20G) process will be available in Q3 2012. In the meantime, TSMC will offer4 versions at 28nm; LP, HPL, G, and HPM. HPM will combine high performance and low power, the sweet spot for ARM cores according to Dr. Chiang.

Dr. Chiang said that the migration to a new process node typically adds 2-3 process modules, but 5 new modules are needed for 20nm. The 20nm process node will be the last generation for planar transistors. The most expensive 20nm process module will be the change to double patterning. TSMC has developed software that will automatically apply DFM requirements to create the 2nd mask from design data.

TSMC’s 20G and 20SoC processes will offer >2X the performance and <0.75X the switching power compared to 28HP & 28HPM. A 20nm SRAM has been fabricated, but 100% yield has not been achieved yet. At 20nm, TSMC is seeing a sidewall interface effect that can dominate interconnect delays, now that line widths are approaching the mean-free path of electrons. According to Dr. Chiang, TSMC has developed a smoothing process that minimizes the effect of electrons literally bouncing off of the walls of interconnect.

TSMC says that they are innovating to extend immersion lithography to 20nm, but that NGL (next-generation lithography) will be required for nodes <20nm. Dr. Chiang said that TSMC plans to have an ASML EUV machine, the NXE-3100 at TSMC by mid-2011.

Nano-KISS: Advanced CMOS Devices

2011-04-01T00:04:00.000-07:00

26-29 April 2011, Palgongsan-DAEGU, Korea

Nano-KISS is organized by Kyungpook National University (KNU) and Grenoble Insitute of Technology (NPG) via World-Class University and Brain Korea 21 projects. Pyeongsan academy, located in the famous Palgong provincial park, is a very attractive place for combining top level lectures with scientific interactions and recreational activities. The first edition in 2010 was dedicated to advanced SOI concepts and technologies. The School topics are changed every year.The program is divided in sub-topics such as to enable full-time participation or single-day participation.

Scientific Program nano-KISS 2011

Build accurate Spice models for low-noise, low-power precision amplifiers

2011-03-22T03:39:00.000-07:00

Build accurate Spice models for low-noise, low-power precision amplifiers: "

System engineers require accurate models for all types of ICs, and they require Spice models to run comprehensive circuit simulations. Early Spice models had few nonlinear elements, minimizing simulation time at the cost of accuracy, but new methods let you increase the number of nonlinear elements and improve accuracy. You can create a multistage model for low-noise, low-power operational amplifiers. The model employs work from Analog Devices (Reference 1) and requires several architectural changes to model a low-noise, low-power precision amplifier. The model architecture processes the input signal through eight stages. You can easily calculate the parameters for the eight stages with a handheld calculator. To understand the model creation, you must have experience using Spice.

Although higher-speed amplifiers have multiple poles and zeros, this model is for a single-pole, 10-MHz amplifier. It lets you simulate the amplifier’s key ac and dc parameters. The model includes ac parameters for flicker and flatband noise, slew rate, CMRR (common-mode rejection ratio), gain, and phase. The model’s dc parameters are VOS (input offset voltage), IOS (input offset current), quiescent supply current, and output-voltage swing. The model uses the 25°C typical parameters (Reference 2). The closer you model the input stage to the actual amplifier, the more accurate your results will be. You can achieve an accurate ac representation of the amplifier’s performance using a few of the process parameters of the input-stage transistors or MOSFETs. This model’s architecture lets you model amplifiers with split supplies. There is no ground reference in any of the signal-processing blocks. After the differential-to-single-ended conversion, all internally generated node voltages are referenced to the midpoint of the power supplies, much like the actual operation of an amplifier."

Complete IC simulation requires a full toolbox of hardware and software

2011-03-22T03:38:00.000-07:00

Complete IC simulation requires a full toolbox of hardware and software: "Discovering a design error after you send youraverage chip to manufacturing c..."

[mos-ak] Final Program MOS-AK/GSA Workshop in Paris

2011-03-16T14:19:00.001-07:00

Please visit the MOS-AK/GSA Paris web site with the final workshop
program:
http://www.mos-ak.org/paris/

* Free On-line Registration Form:
http://www.mos-ak.org/paris/registration.php

* Venue:
Université Pierre et Marie Curie
LIP6 (UPMC)
4 Place Jussieu; Paris
Bâtiment ESCLANGON; Amphithéâtre ASTIER

* Agenda: 7-8 April 2011 MOS-AK/GSA Workshop
"Frontiers of the Compact Modeling for Advanced Analog/RF
Applications"

April 7 (13:00-16:00)
* half day/afternoon MOS-AK modeling session
* poster session introduction
* COMON Network meeting/session (members only)
* informal MOS-AK/COMON "modeling" dinner (individual selfpaid)

April 8 (9:00-16:00)
* morning MOS-AK Session
* poster session
* afternoon MOS-AK Session

2011-03-14T02:57:00.000-07:00

I've found this offer, which I'm sharing with you:

Looking for Modeling & Characterization Engineer. Please send resume to Goldie.Homan@onsemi.com or apply Job 10536 at http://www.onsemi.com/PowerSolutions/content.do?id=16367

Position Description As a Modeling Engineer in the Corporate R&D department, you will:

- Perform and analyze electrical measurements on various devices.
- Design test structures.
- Extract device SPICE models using ICCAP, UTMOST, MQA, and other in-house software packages.
- Support transfer methodology for models from TRD to Design Methodology.
- Document characterization and modeling work according to established procedures.
- Evaluate and support implementation of new characterization, modeling and methods.
- Provide performance assessment and feedbacks for device development engineering.
- Interface with Design Methodology, Design, Foundry and external customers to resolve characterization/modeling issues and improve characterization/modeling methods.
- Work jointly with modeling groups in CZ to perform characterization/modeling tasks.
- Perform other tasks as may be from time to time assigned.

Position Requirements Successful candidates for this position will have:

- A BS/MS/PhD in Electrical Engineering/Physics/Material Science/Chemical Engineering/Chemistry. MS/PhD preferred.
- In-depth understanding of semiconductor device physics and proficiency in DC, AC, and RF characterization.
- Previous Design/Device fabrication/Process integration experience desired.
- Ability to utilize statistical techniques is required.
- UNIX/LINIX shell, PERL programming experience is desired.
- Previous experience with BiPolar device design/simulation/modeling is a plus.
- Previous experience in RF parasitic extraction is a plus
- Demonstrated ability to work successfully with external groups is required.

Expiring in 11 days(March 25th, 2011)

ON Semiconductor: Search for Careers Worldwide onsemi.com

NASA To Host Open Source Summit

2011-03-13T04:14:00.000-07:00

NASA will host a summit about open source software development on March 29-30 at the agency's Ames Research Center in Moffett Field, Calif. The event runs from 9 a.m. to 5 p.m. PDT on both days.

NASA's first Open Source Summit will bring together engineers, policy makers and members of the open source community. Participants will discuss the challenges within the existing open source policy framework and propose modifications to facilitate NASA's development, release and use of software. [more]

SPICE: a 40-year old open-source success story

2011-03-02T03:32:00.000-08:00

From EDN:

SPICE: a 40-year old open-source success story
SPICE, the Simulation Program with Integrated Circuits Emphasis, has turned 40 years old. The IEEE has marked the occasion by designating the development of SPICE as a Milestone in Electrical Engineering and Computing. On February 23rd, the Computer History Museum hosted a celebration with a roundtable discussion by the individuals most responsible for bringing SPICE from its origin as a UC Berkeley student project to the huge commercial success it has achieved as the most widely used tool in the semiconductor industry.

The panel (from left to right) consisted of:

Ron Rohrer - 2002 Kaufman Award recipient, who taught the class at UCB that developed the progenitor of SPICE, CANCER (Computer Analysis of Nonlinear Circuits, Excluding Radiation)
Larry Nagel - as a student in Ron’s class, Larry took on CANCER as his Master’s degree project, and eventually developed the 1st successful implementation - SPICE2 - as his doctoral thesis.
Kim Hailey - co-founder (with Shawn Hailey) of Meta-Software, where HSPICE was created.
Ken Kundert - who led the development of Cadence’s Spectre simulator.
David Hodges - Distinguished Professor Emeritus at UCB, the panel moderator, who is well known for leading the development of analog IC design in CMOS and for the original (Level-1) Shichman-Hodges MOS device model.

Analog/Mixed-Signal Behavioral Modeling

2011-02-28T02:39:00.000-08:00

From Cadence... (see the original)

Analog/Mixed-Signal Behavioral Modeling – When to Use What

By Richard Goering on February 20, 2011

So when to use what? The conservative style provided by Verilog-A and Verilog-AMS is useful when there are significant accuracy requirements. This approach can potentially provide a 50-100X speedup over SPICE, but it all depends on how good your modeling is. "If you're a poor modeler, there's a chance you could end up with a model that's as slow as SPICE simulation or even slower," Walter warned.
Real number modeling, also available through Verilog-AMS with the wreal data type, brings real number values into event-driven digital simulation. It thus has the speed benefits of digital simulation and can leverage the metric-driven verification methodology that's increasingly used by digital engineers. It's good when there are hard performance requirements and limited accuracy requirements. For example, wreal is very useful for full-chip mixed-signal simulations.
The following chart shows the accuracy/speed tradeoff ranges provided by various analog/mixed-signal modeling alternatives. Note that the conservative modeling style has a broad possible range, depending on how good the modeling is.
Also important is the modeling effort. Here we can see that conservative models require the most amount of effort. "You can potentially spend days, weeks, months to develop good behavioral models," Walter said. Wreal models are relatively fast to develop because they're less detailed. An important rule of thumb: "Model what you need, not what you can."

Microelectronics Journal, in-press, february 2011

2011-02-25T05:30:00.000-08:00

Modeling of threshold voltage of a quadruple gate transistor

Md. Gaffar, Sayed Ashraf Mamuna, and Md. Abdul Matina

Available online 24 February 2011.
Abstract

In this paper, a three dimensional analytical solution of electrostatic potential is presented for undoped (or lightly doped) quadruple gate MOSFET by solving 3-D Poisson's equation. It is shown that the threshold voltage predicted by the analytical solution is in close agreement with TCAD 3-D numerical simulation results. Numerical simulation, self-consistent Schrodinger–Poisson equations, calibrated by 2D non equilibrium green function simulation, are used.

The First Full-Color Display with Quantum Dots

2011-02-23T00:25:00.000-08:00

Rodrigo Picos (rpicosg@gmail.com*) has sent you an article from TechnologyReview.com!

Click below to read the article:

The First Full-Color Display with Quantum Dots
Samsung's new four-inch display could eventually lead to flexible screens.
By Prachi Patel

If clicking on the title above does not work, paste the link below into your web browser:
http://www.technologyreview.com/computing/32407/

*The sender's identity has not been verified. Click here to read Technology Review's Privacy Policy.

SPICE Circuit Simulator Named IEEE Milestone

2011-02-22T23:30:00.000-08:00

Simulating a circuit with SPICE is the industry-wide standard way to verify operation at the transistor level before manufacturing an IC. The program has become so ubiquitous that engineers often say they are going to “SPICE a circuit” when they are about to test one. To mark the 40th anniversary of SPICE—the Simulation Program with Integrated Circuit Emphasis—IEEE has designated its creation an IEEE Milestone in Electrical Engineering and Computing.

SPICE was made publicly available in 1971 so that chip designers could modify it—an early example of open-source software. Two years later, SPICE became well known after it was described in a paper by Pederson at the 16th Midwest Symposium on Circuit Theory, in Waterloo, Ont., Canada. During the next few years, developers around the world began using and modifying SPICE, leading it to become the industry standard it is today. “What happened was truly phenomenal,” Nagel wrote in “The Origins of SPICE.” “Within a few years, SPICE had achieved acceptance at almost all electrical engineering schools [for use in teaching] and had [spawned] a cottage industry to supply SPICE derivatives to the rapidly expanding integrated circuit industry.”

[Read more by Anna Bogdanowicz @ IEEE]

Papers in SSE (vol 57 , issue 1, March 2011)

2011-02-15T00:17:00.000-08:00

Analytical threshold voltage model for lightly doped short-channel tri-gate MOSFETs

A. Tsormpatzoglou, D.H. Tassis, C.A. Dimitriadis, G. Ghibaudo, N. Collaert, G. Pananakakis

Generic complex-variable potential equation for the undoped asymmetric independent double-gate MOSFET

Adelmo Ortiz-Conde, Francisco J. García-Sánchez

Research highlights

► Single completely generic equation of channel potential for undoped asymmetric independently driven double-gate MOSFETs. ► Channel potential equation is based on complex variables and is valid for all values of front and back-gate bias. ► The unified nature of the proposed equation provides a better basis for global physical insight. ► Several examples, including the all important fully symmetric case, are analyzed.

Compact modeling of CMOS transistors under variable uniaxial stress

Nicoleta Wacker, Harald Richter, Mahadi-Ul Hassan, Horst Rempp, Joachim N. Burghartz

Research highlights

► We propose a method to simulate the effect of uniaxial stress on MOSFETs. ► The method is valid for any drain current and stress directions in (001) Si plane. ► It can perform static and dynamic simulations, in linear and saturation regions. ► It is simulator-independent and does not depend on the source of uniaxial stress. ► It is adaptable to other bulk CMOS nodes and to other technologies such as SOI.

A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

F. Lime, R. Ritzenthaler, M. Ricoma, F. Martinez, F. Pascal, E. Miranda, O. Faynot, B. Iñiguez

Research highlights

► Valid for long-channel undoped ADGMOSFETS with independent gate operation. ► Fully analytical and explicit derivation with no iterative solutions. ► Accessible front and back gate charges, potentials and currents. ► Unification of symmetric and asymmetric cases. ► Physical solutions similar to classical MOS theory.

In-depth physical investigation of GeOI pMOSFET by TCAD calibrated simulation

B. Grandchamp, M.-A. Jaud, P. Scheiblin, K. Romanjek, L. Hutin, C. Le Royer, M. Vinet

Research highlights

► We performed 2D simulations of germanium-on-insulator fully-depleted pMOSFET. ► Interface traps, mobility and leakage were calibrated versus experimental data. ► The prediction of electrical characteristics is accurate for several gate lengths. ► These simulations help in finding guidelines for improving the on-state current.

Mobility in ultrathin SOI MOSFET and pseudo-MOSFET: Impact of the potential at both interfaces

G. Hamaide, F. Allibert, F. Andrieu, K. Romanjek, S. Cristoloveanu

Research highlights

► Biasing the back interface in accumulation while extracting carrier mobility in FD-SOI MOSFETs leads to underestimated values. ► Apparent mobility degradation with decreasing film thickness in ultra-thin SOI MOSFET or Pseudo-MOSFET measurement is due to an additional component of the vertical electric field. ► In Pseudo-MOSFET measurements, the additional component of the vertical electric field comes from the traps and charges at the free-surface of the sample. ► We propose a new model to take this additional component of the vertical electric field into account.

Is SPICE good enough for tomorrow's analog?

2011-02-14T02:24:00.000-08:00

by Nagel, L.W.; McAndrew, C.C.;
IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2010),
Digital Object Identifier: 10.1109/BIPOL.2010.5668096
Publication Year: 2010 , Page(s): 106 - 112

"The answer to the question posed in the title is an emphatic yes! Because SPICE is fairly general purpose and is not tied to any particular technology (not even only semiconductors), SPICE will play a significant role in the design of integrated circuits for a long time. SPICE will not be used to simulate billion transistor circuits, of course, but instead it will play a key role in developing the devices, device models, building blocks, and behavioral models for the building blocks for the billion transistor chips. SPICE will continue to play the role of the foundation of the integrated circuit design infrastructure." [Nagel, L.W.; McAndrew, C.C.]

[mos-ak] C4P MOS-AK/GSA Workshop at UPMC/LIP6 Paris on 7-8 April 2011

2011-02-07T12:41:00.001-08:00

C4P MOS-AK/GSA Workshop at UPMC/LIP6 Paris on 7-8 April 2011
http://www.mos-ak.org/paris/

Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop at
UPMC/LIP6 Paris on 7-8 April 2011

The MOS-AK/GSA Workshop is HiTech forum to discuss the frontiers of
the electron devices modeling with emphasis on simulation-aware
models. Original papers presenting new developments and advances in
the compact/spice modeling and its Verilog-A standardization are
solicited. The main topics of the workshop are: (but are not limited
to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Reliability and thermal management of electron devices
* Technology R&D, DFY, DFT and IC designs
* Foundry/Fabless interface strategies

The terms of participation:
Authors are asked to submit a short (~200words) abstract using on-line
submission form by MARCH.1st:
http://www.mos-ak.org/paris/abstracts.php

Intending authors should also note the following deadlines:
* Call for Papers - Feb.2011
* Notification of preliminary acceptance - March 2011
* Final Workshop Program - end of March 2011
* MOS-AK/GSA Workshop - 7-8 April 2011

Further details and updates http://www.mos-ak.org/paris/
On-line workshop registration http://www.mos-ak.org/paris/registration.php

Local Organizing Committee:
Marie-Minerve Louerat, UPMC/LIP6
Ramy Iskander, UPMC/LIP6

Technical Program Committee:
Marie-Minerve Louerat, UPMC/LIP6
Andrei Vladimirescu, ISEP/UCB
Costin Anghel, ISEP
Ramy Iskander, UPMC/LIP6

Extended MOS-AK/GSA Committee:
Lisa Tafoya, Vice President, Global Semiconductor Alliance (GSA)
Chelsea Boone, GSA; Director of Research
Kayal Rajendran, GSA; Senior Research Analyst
Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster
Roberto Tinti, Agilent EEsof Division
MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil
Sergio Bampi, UFRGS, Brazil
Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Alexander Petr, XFab
Co-Chair: Prof. Benjamin Iniguez, URV
James Victory, Sentinel-IC
MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Xing Zhou, NTU, Singapore
A.B. Bhattacharyya, JIIT, India

IEEE SCV EDS: February 8 Photovoltaic Technology Talk

2011-02-07T02:40:00.000-08:00

Talk on photovoltaic technology on Feb. 8th. Module reliability is a key issue in photovoltaic technology.

Feb 8th:

Dr. Glenn Alers – UC Santa Cruz,

“Photovoltaic Module Reliability and Failure Analysis: Enduring a storm”

(Next month event) March 1st:

Dr. Geert Vandenberghe, IMEC,

“Lithography Options for 22nm and Beyond”

More information at the IEEE Santa Clara Valley EDS Chapter Home Page
http://www.ewh.ieee.org/r6/scv/eds/

Molybdenite touted as 'material to revolutionize electronics'

2011-02-03T00:21:00.000-08:00

Molybdenite touted as 'material to revolutionize electronics': "A material called molybdenite is being touted by researchers as having distin..."

High school teacher creates microfluidic devices using a photocopier

2011-01-30T09:24:00.000-08:00

Photo courtesy Harvard University [read more]

Postdoc position on compact device modeling in Spain

2011-01-28T12:02:00.000-08:00

As Professor in the Universitat Rovira i Virgili (Tarragona, Spain), I am going to apply for a postdoctoral position (funded by the Spanish Ministry under the Programa Juan de la Cierva) related to the European projects we participate in: the SQWIRE project (a project about technology, characterization and modeling of Si nanowires) and the Compact Modeling Network, COMON (of which I am the coordinator).

The candidate should be a person who holds a PhD as awarded within the three years prior to the date when the period for presentation of application forms closes. The Ph D must have been obtained later than January 1 2007. If the candidate does not hold a PhD yet, the deadline to be awarded a PhD is the date of publication of the Awarding Resolution in the Ministry of Education and Science web site.

The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. In any case, it will be related to the European projects in which we participate. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by these European projects: nanowire FETs, multi-gate MOSFETs (FinFETs, DG MOSFETs,...), High Voltage MOSFETs and advanced HEMTs.

The postdoc position, which will be a contract, will have a duration of up to 3 years. The net salary will be around 1900 Euro/months.

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: February 8 2011

MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat

Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona
SPAIN.

About Tarragona:

Tarragona is located on the Mediterranean, in the heart of the Costa Daurada, in the south of Catalonia, about 100 Km south from Barcelona. Tarragona is well connected to Barcelona by highway, and frequent trains and buses. It has also a direct bus connection with Barcelona Airport. Besides, it has high-speed rail connection with Madrid and Barcelona.

Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. F On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public. Among the citizens of Tarragona, it has moreover fomented knowledge of, pride in and respect for the city.

Speaking about Tarraco’s climate, the famous Roman poet Virgil wrote: “The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring.” Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe. The city has a population of 120,202 inhabitants, and the native tongue is Catalan, but everybody speaks also Spanish, which is also official in Catalonia. Many people can also speak English (especially the young people) or French.

Papers in SSE (vol 56, issue 1, february 2011)

2011-01-21T00:14:00.000-08:00

Temperature model for Ge₂Sb₂Te₅ phase change memory in electrical memory device Original Research Article

Pages 13-17
Daolin Cai, Zhitang Song, Houpeng Chen, Xiaogang Chen

Research highlights

► Temperature model is constituted by an active region and a dispersed-heat region. ► Calculated and simulated the radius and crystalline fraction. ► Crystalline fraction and temperature increase with the reset voltage increasing.

Microwave noise modeling of FinFETs Original Research Article

Pages 18-22
Giovanni Crupi, Alina Caddemi, Dominique M.M.-P. Schreurs, Wojciech Wiatr, Abdelkarim Mercha

Comprehensive numerical simulation of threshold-voltage transients in nitride memories Original Research Article

Pages 23-30
Aurelio Mauri, Salvatore M. Amoroso, Christian Monzio Compagnoni, Alessandro Maconi, Alessandro S. Spinelli

Research highlights

► We present a complete model to describe charge trap devices behavior. ► In this study any mathematical aspect regarding holes and electrons is detailed modeled. ► Experimental data coming from different TANOS and SONOS devices are correctly reproduced.

A unified short-channel compact model for cylindrical surrounding-gate MOSFET Original Research Article

Pages 40-46
Bastien Cousin, Marina Reyboz, Olivier Rozeau, Marie-Anne Jaud, Thomas Ernst, Jalal Jomaah

Research highlights

► A compact model of short-channel effects for GAA MOSFET has been developed. ► The model uses a well-known extraction method making the model simple and accurate. ► Each term is used in a model core in order to provide a short-channel correction. ► The compact model is well described and is suitable with circuit design tools. ► The model is validated using TCAD simulations for all gate lengths down to 10nm.

Physical limitations of the diffusive approximation in semiconductor device modeling Original Research Article

Pages 60-67
Tigran T. Mnatsakanov, Alexey G. Tandoev, Michael E. Levinshtein, Sergey N. Yurkov

Research highlights

► New criteria for occurrence of the diffusion mode were formulated. ► The applicability limits of the diffusion approximation in simulation were found. ► The analytical results are confirmed by a numerical experiment.

Direct determination of threshold condition in DG-MOSFETs from the g_m/I_D curve   Original Research Article

Pages 89-94
Ana Isabela Araújo Cunha, Marcelo Antonio Pavanello, Renan Doria Trevisoli, Carlos Galup-Montoro, Marcio Cherem Schneider

Dynamic model of AlGaN/GaN HFET for high voltage switching   Original Research Article

Pages 135-140
Alexei Koudymov

A surface potential based drain current model for asymmetric double gate MOSFETs   Original Research Article

Pages 148-154
Pradipta Dutta, Binit Syamal, N. Mohankumar, C.K. Sarkar

Research highlights

► We model a surface potential based drain current for asymmetric DG MOSFETs. ► The model is applicable for both heavily and lightly doped Silicon channel. ► The surface potential at both the gates are solved using proper Iterative techniques. ► The effect of volume inversion is shown in case of lightly doped channel.

AlGaN/GaN hybrid MOS-HEMT analytical mobility model Original Research Article

Pages 201-206
A. Pérez-Tomás, A. Fontserè

Research highlights

► The hybrid normally-off switch AlGaN/GaN MOS-HEMT combines two main advantages: ► The MOS gate control and the high 2DEG mobility in AlGaN/GaN drift region. ► Here, we present simple analytical modeling of the on-resistance of a hybrid MOS-HEMT. ► We investigate the layout, the MOS channel mobility, the effect of a high-k and the temperature. ► The model can aid to understand the device physics and is compatible with TCAD simulation packages.

Mobility degradation and transistor asymmetry impact on field effect transistor access resistances extraction

Pages 214-218
J.C. Tinoco, A.G. Martinez-Lopez, J.-P. Raskin

[uSG] New Website

2011-01-20T00:24:00.000-08:00

Microelectronics Students' Group website is finished and can be visited at: http://usgroup.eu where you can also find out more about usgroup, as well as their projects and activities. You can also follow usgroup on Twitter and on Facebook. For further information please contact:

Daniel Oliveira (Microelectronics Students' Group)
Faculdade de Engenharia da Universidade do Porto
Rua Dr. Roberto Frias, s/n 4200-465 Porto PORTUGAL

mail: cmos@fe.up.pt, web: cmos.fe.up.pt

[mos-ak] 8th IWCM; Jan.25, 2011; Pacifico Yokohama, Japan

2011-01-17T05:34:00.000-08:00

8th International Workshop on Compact Modeling
http://www.aspdac.com/aspdac2011/colocated_event/
January 25(Tue), 2011
Pacifico Yokohama room 419, Yokohama, Japan

The workshop provides an opportunity for the discussion and the
presentation of advances in modeling and simulation of integrated
circuits. Following IWCM sessions are foreseen:

Workshop Opening: M. Miura-Mattausch (chair)
Simulation Methodology (Chair: Z. Yu)
Conventional MOSFET (Chair: G. Yokomizo)
Organic Materials (Chair: W. Grabinski)
Power Device (Chair: Y. J. Park)
Closing: J. He (co-chair)

Complete IWCM program is available on-line:
http://home.hiroshima-u.ac.jp/usdl/IWCM/FILES/IWCM_Program_11_revised.pdf

[mos-ak] MOS-AK/GSA San Francisco Workshop Press Release

2011-01-12T14:54:00.001-08:00

Press release:
MOS-AK/GSA Modeling Working Group Holds Workshop in San Francisco
Experts Share Insight on Electron Device Modeling with Emphasis on
Simulation-Aware Models
can be found on the GSA site at: http://www.gsaglobal.org/news/article.asp?article=2011/0110

Opprtunity with MNC Product Company in Bangalore

2011-01-09T23:20:00.000-08:00

I copy a post from LinkedIn:

Position Description
The member of technical staff (MTS) in this role will be responsible for the implementing and maintaining all device models for the company’s Analog FastSPICE (AFS) circuit simulator. The MTS will also debug various model-related circuit simulation issues such as convergence and accuracy issues, which will require working closely with circuit simulation developers and application engineers. The successful candidate will have sufficient circuit and circuit simulator background for these responsibilities.

Responsibilities

Implement and maintain all device models for the AFS circuit simulator.
Improve performance, convergence, and similar issues related to device models.
Verify device model accuracy and create testcases to validate and regression test accuracy.
Develop and maintain interfaces to implement models from Verilog-A and other simulators.
Lead AFS circuit simulator qualification for various foundry process technologies.
Work with applications and customers on select model and model interface development.
Requirements

3+ years experience in areas related to model development and circuit simulation.
Excellent knowledge of circuits containing diode, bipolar, and MOS devices.
Experience in debugging customer test cases for model and model related issues.
Good knowledge of Verilog-A and modeling in Verilog-A.
Outstanding programming skills in C/C++.
Excellent oral and written communication skills.
Ability work effectively within a worldwide development organization.
Masters or PhD degree in electrical engineering or relevant area.
Desirable

Familiarity with architecture of model implementation in true SPICE accurate simulators.
Previous experience in implementing device models in a circuit simulator.

Interested folks can contact bibin.sundaran at careernet.co.in, 9611833167

[mos-ak] MOS-AK/GSA San Francisco, CA Workshop on-line Publications

2010-12-20T13:16:00.000-08:00

MOS-AK/GSA San Francisco, CA workshop on-line publications are
available, visit:
http://mos-ak.org/california/

More that 50 registered participants followed 11 technical compact
modeling talks at the MOS-AK/GSA Compact Modeling Workshop in San
Francisco, CA. I would like to thank all MOS-AK/GSA speakers for
sharing their compact modeling competence, R&D experience and
delivering valuable MOS-AK/GSA presentations. I am sure, that our
modeling event in San Francisco, CA was beneficial to all MOS-AK
Workshop attendees.

Organization of our modeling event would not be possible without our
generous sponsors: Accelicon Technologies and Cascade Microtech as
well as the IEEE EDS, technical co-sponsorship. I also would also like
to personally acknowledge local workshop organizers, in particular,
Tim K. Smith for his dedication and personal assistance to provide
smooth workshop logistics.

I hope, we would have a next chance to meet us with your academic and
industrial partners at future MOS-AK/GSA modeling events (check the
list below).

- with regards - WG (for the MOS-AK/GSA Committee)
––––––––––––––––––––––––––––––––––----------------
MOS-AK/California on-line publications <http://mos-ak.org/california/
>
MOS-AK/Seville on-line publications <http://mos-ak.org/seville>
IWCM at ASP-DAC in Yokohama Jan.2011 (with MOS-AK Support)
MOS-AK/Paris at UPMC/LIP6 <http://www.mos-ak.org/paris/>
MIXDES in Gliwice June 16-18, 2011 (with MOS-AK Session)
MOS-AK/Helsinki Sept.16, 2011 (ESSDERC time frame)
––––––––––––––––––––––––––––––––––----------------

Electronics industry braces for rare-earth-materials shortages

2010-12-15T00:43:00.000-08:00

From EDN:

Electronics industry braces for rare-earth-materials shortages:

"China has started to severely restrict the exports of rare-earth materials, which often find use in “green”-technology designs, including hybrid vehicles and energy-efficient lighting, as well as in the medical, defense, and consumer markets. The country delivers nearly 100% of the world’s rare-earth materials: 17 metals that are somewhat hard to refine and that tend to occur in the same ore deposits (Table 1). The cutbacks have resulted in shock waves through the electronics industry and could force design changes in the near future.

China set out on a moderate restriction path this year and then announced in July that it would cut exports by 72% for the remainder of 2010. It plans an overall export reduction of 30% for next year.

These cutbacks have increased the price of rare-earth materials an average of 700%, prompting legislation, which is currently stalled, to restart US rare-earth-materials production. The Western Hemisphere’s one rare-earth-materials producer, Colorado-based Molycorp Minerals, issued an initial public offering of stock in July, raising $390 million to restart its California mine and ramp up processing to counter world shortages.

Part of China’s motivation for reducing rare-earth-materials exports is its desire to emphasize its industrial status. China’s leaders want to move away from raw-materials exports and evolve toward exporting more finished goods.

Production of rare-earth materials fell off worldwide beginning in the 1980s when low prices in China made production unfeasible elsewhere in the world. Tom Valiere, senior vice president and co-founder of Design Chain Associates, says this cutback is a wake-up call for US industry. “We used to lead the world in the export of rare-earth materials,” he says. “In the last 20 years, we’ve become dependent. The whole thing flew under the radar until green technology placed demand on rare-earth materials and we realized they were sole-sourced to China.”

China’s restrictions this year have been part of a multiyear plan to save most of its supply for its own industry. “Each year, China has brought down its exports by X% and never exceeded its quotas,” says Gareth Hatch, co-founder of Technology Metals Research. “The reduction the country made in July was a huge reduction over the first half of the year.”

Worldwide shortages are now occurring. “The world outside China uses a collective 50,000 tons annually,” says Jim Simms, director of public affairs at Molycorp Minerals. “[China] reduced its exporting in 2010 to about 30,000 tons. Since China supplies about 97% of rare-earth materials, the world has to depend on what China exports.”

Simms believes that the demand for the materials will just increase over the coming years. The company expects to produce 20,000 tons by the end of 2012. “My BlackBerry only has about 3/10g of rare-earth materials,” he says, but “a single wind turbine requires about one ton. A car can use about 25 kg.”

Lynas Corp, a rare-earth-materials supply company in Australia, expects to increase rare earths delivery in 2011 to 11,000 tons per year.

Rare-earth materials facts

Rare-earth materials include terbium, which finds use in flat-panel TVs and high-efficiency fluorescent lamps, and neodymium, key to the permanent magnets in high-efficiency electric motors. Rare-earth materials are not indeed rare. The series of nonferrous metals is common in the environment. According to Design Chain Associates, most rare-earth materials are as common as copper, and even the rarest is more common than gold.

Part of the market pressure on rare-earth materials comes from new demand that green technologies has prompted. The market, including electric- and hybrid-vehicle motors and wind turbines, requires magnets.
,..."

WOCSDICE'2011

2010-12-15T00:41:00.001-08:00

The abstract submission for the 35th edition of the European "Workshop on Compound Semiconductor Devices and Integrated Circuits" (WOCSDICE 2011) is open.
The conference will be held in Catania (Italy), from May 29th to June 1st 2011.

Short abstracts, not exceeding 300 words, must be submitted via e-mail at the following address: abstract@wocsdice2011.org
Detailed guidelines for abstract preparation and submission can be found on the conference website (www.wocsdice2011.org) under the session "Abstract Submission". In the website you will find also other practical information concerning the registration and accommodation.

The dead line for short abstracts submission is February 25th, 2011.

Authors will be notified by March 21st, 2011 regarding the status of their paper by e-mail.
For the accepted contributions, an extended abstract, maximum 2 pages of length (4 pages for invited speakers), including figures, tables and references, will be required within April 11th, 2011.

8.3% Efficiency in a OPV

2010-12-09T01:13:00.000-08:00

I copy from their webpage:

Konarka's Power Plastic Achieves World Record 8.3% Efficiency Certification from National Energy Renewable Laboratory (NREL)

Lowell, Mass. - Nov. 29, 2010 - Konarka Technologies, Inc., an innovator in development and commercialization of Konarka Power Plastic®, a material that converts light to energy, today announced that the National Energy Renewable Laboratory (NREL) has certified that Konarka’s organic based photovoltaic (OPV) solar cells have demonstrated a record breaking 8.3% efficiency. This is the highest performance recorded by NREL for an organic photovoltaic solar cell.
"The progress Konarka has achieved this year with regard to solar cell efficiency is unprecedented, representing a significant milestone for the industry," commented Howard Berke, chairman, CEO and co-founder of Konarka. "This unsurpassed NREL certification opens new doors for the commercial production of cost-effective, efficient electricity for numerous large scale applications."
Konarka Power Plastic is a patent-protected thin film solar material that converts light to energy. The unique material is lightweight and flexible, lending itself to a wide range of applications where traditional photovoltaics are not effective.
The latest certification results are for Konarka’s large area single-junction solar cell with a surface area of 1 square centimeter. This efficiency rating far exceeds previous single-junction organic photovoltaic cell measurement on that surface area and represents the world record for OPV efficiency.

24th International Conference on Microelectronic Test Structures (ICMTS)

2010-12-02T00:12:00.000-08:00

The IEEE Electron Devices Society sponsors the 24th International Conference on Microelectronic Test Structures (ICMTS).

The conference will be held on April 5-7, 2011, in downtown Amsterdam (The Netherlands) at the Royal Academy of Arts and Sciences, and will be preceded by a one-day Tutorial Short Course on Microelectronic Test Structures on April 4. The program further includes a company exhibit and various social events in and around the Academy.

Registration to the conference is now open. If you wish more info, please visit their website http://icmts2011.ewi.utwente.nl/ for further information.

[mos-ak] Final Program MOS-AK/GSA Workshop in San Francisco

2010-11-29T14:27:00.001-08:00

Please visit the MOS-AK/GSA San Francisco web site with the final
workshop program:
http://www.mos-ak.org/california/

* Free On-line Registration Form:
http://www.mos-ak.org/california/registration.php

* Venue: The JW Marriott Union Square, San Francisco, CA
http://www.marriott.com/hotels/travel/sfojw-jw-marriott-san-francisco-union-square/

* Agenda
Dec. 8, 2010: MOS-AK/GSA Workshop co-located with the CMC Meeting and
IEDM Conference
9:00 - 12:00: Morning Session - Chair: Ian Getreu
13:00 - 16:00: Afernoon Session - Chair: Larry Nagel
http://www.mos-ak.org/california/

MOS-AK/GSA Happy Hour at Noma Gallery
after 18:00 - Discussion, networking and...
80 Maiden Ln. 3rd fl, San Francisco, CA
http://www.nomagallerysf.com/artists/NOMA_GALLERY/index.html

Senior Research Engineer - MEMS circuits

2010-11-10T00:22:00.000-08:00

Responsibilities:

Electro-mechanical computing has recently emerged as a very promising solution for ultra-low-power and high temperature circuit applications. The candidate will be responsible of the development of nano-electromechanical components for computation applications (logic and memory devices). This research will include device physics and modeling, design, fabrication in the IME cleanroom and characterization of electro-mechanical devices and circuits. Reliability and failure testing of memory arrays will be conducted.

Requirements:

PhD degree in Mechanical Engineering, Electrical Engineering or Material Sciences. Hands-on experience on wafer level MEMS related works, including microfabrication process and work in a cleanroom environment. Familiar with electrical measurement techniques (device and memory arrays). Strong interest for MEMS multi-physics modeling. Excellent communication skills and teamwork with strong self-motivation. Interaction with industrial/academic partners expected.

Please contact Dr Vincent Pott for more information.

Position to remain open until a candidate is selected (apply online).

First comprehensive and systematic course on statistical variability

2010-11-02T02:52:00.000-07:00

I am delighted to bring to your attention the first comprehensive and systematic course on statistical variability.

Dates: 11-12 January 2011 in Grenoble.

This first edition of the course is in collaboration with the SINANO Institute and the FP7 NoE NANOSIL.

The course covers:

· Variability classification
· Sources of statistical variability
· Simulation of statistical variability
· Variability trends in conventional and novel MOSFETs
· Random telegraph noise statistics
· Statistical aspects of reliability
· Statistical compact model strategies
· Statistical circuit simulation

You can find the syllabus at:
http://www.goldstandardsimulations.com/courses/syllabus/

You will be able to register for the course soon at:

http://www.goldstandardsimulations.com/courses/.

[mos-ak] C4P MOS-AK/GSA Workshop in San Francisco on December 8th, 2010

2010-11-01T16:42:00.000-07:00

C4P MOS-AK/GSA Workshop in San Francisco on December 8th, 2010
http://www.mos-ak.org/california/

We, together with the lead sponsors Accelicon Technologies and Cascade
Microtech, are delighted to declare that we have confirmed a first-
class location for the MOS-AK/GSA Workshop in San Francisco on
December 8th, 2010: the JW Marriott Union Square <http://
www.marriott.com/hotels/travel/sfojw-jw-marriott-san-francisco-union-square/>.
Attendees will need to secure their own lodging and transportation to
the event. The JW Marriott is centrally located near Union Square,
near IEDM, and public transportation is abundant.

The MOS-AK/GSA Workshop in San Francisco will be organized as in the
timeframe of the IEDM and CMC Meetings. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies

On-line abstract submission will be open on Nov.5, 2010.

Further details and updates http://www.mos-ak.org/california/

Local Organizing Committee:
Junko Nakaya, Cascade Microtech
Tim K.Smith, Accelicon Technologies

Extended MOS-AK/GSA Committee:
Jodi Shelton, President, Global Semiconductor Alliance (GSA)
Chelsea Boone GSA; Senior Research Analyst
Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster
Co-Chair: Roberto Tinti, Agilent EEsof Division
MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil
Co-Chair: Sergio Bampi, UFRGS, Brazil
Co-Chair: Prof. Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Alexander Petr, XFab
Co-Chair: Prof. Benjamin Iniguez, URV
Co-Chair: James Victory, Sentinel-IC
MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Prof. Xing Zhou, NTU, Singapore
Co-Chair: Prof. A.B. Bhattacharyya, JIIT

PRIME 2011 Conference

2010-10-29T06:34:00.000-07:00

4-8 July 2011, Madonna di Campiglio (TN), Italy

The main objectives of PRIME 2011 Conference are:

to encourage favorable exposure to Ph.D. students in the early stages of their careers
to benchmark Ph.D. research in a friendly and cooperative environment
to enable sharing of student and supervisor experiences of scientific and engineering research
to connect Ph.D. students and their supervisors with companies and research centers

Paper Submission

The PRIME 2011 conference will allow only electronic submission of papers in PDF format (maximum file size must not exceed 2 Mbytes). Papers must not exceed four A4 pages with all illustrations and references included. The quality of the conference will be guaranteed by a thoroughly selected Technical Program Committee, which will provide detailed feedback to the authors. The accepted papers in the final camera ready format will be available on IEEE Xplore database. Papers submission will be opened during the first week of January, 2011. Manuscript guidelines as well as instructions on how to submit electronically your paper will be available soon on the conference web page.

E-mail: prime2011@fbk.eu
Website: http://prime2011.fbk.eu/

14 inch Transparent OLED Display Notebook from Samsung mobile

2010-10-29T00:14:00.000-07:00

I couldn't resist the temptation to share this...

TriQuint rolls new GaAs foundry process

2010-10-28T01:24:00.000-07:00

RF chip maker TriQuint Semiconductor Inc. has released its latest 150-mm gallium arsenide (GaAs) commercial foundry process. The process, dubbed TQP15, is targeted at the Ka-band segment. It is designed for building millimeter wave (mmWave) MMICs for applications such as VSAT, satellite communications and point to point radios [read more...]

New papers (October 27, 2010)

2010-10-27T00:36:00.000-07:00

Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis (abstract)
Separate Extraction of Source, Drain, and Substrate Resistances in MOSFETs With Parasitic Junction Current Method (abstract)
A Physics-Based Compact Model for Polysilicon Resistors (abstract)
The Equivalent-Thickness Concept for Doped Symmetric DG MOSFETs (abstract)
An Analytical I–V Model for Surrounding-Gate Transistors That Includes Quantum and Velocity Overshoot Effects (abstract)
Failure of the Scalar Dielectric Function Approach for the Screening Modeling in Double-Gate SOI MOSFETs and in FinFETs (abstract)
Device Physics and Characteristics of Graphene Nanoribbon Tunneling FETs (abstract)
Analytical Threshold Voltage Model Including Effective Conducting Path Effect (ECPE) for Surrounding-Gate MOSFETs (SGMOSFETs) With Localized Charges (abstract)

And other papers that I've found interesting:

Dual Threshold Voltage Organic Thin-Film Transistor Technology (abstract)
Complementary Organic Circuits Using Evaporated $ hbox{F}_{16}hbox{CuPc}$ and Inkjet Printing of PQT (abstract)
Low-Voltage High-Performance Pentacene Thin-Film Transistors With Ultrathin PVP/High- $kappa$ HfLaO Hybrid Gate Dielectric (abstract)
High-Performance Pentacene Thin-Film Transistors Fabricated by Organic Vapor-Jet Printing (abstract)
Magnetic-Field Area Sensor Using Poly-Si Micro Hall Devices (abstract)
On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits (abstract)
On Undetectable Faults and Fault Diagnosis (abstract)

Job offers in LinkedIn: RF Modeling Device Engineer

2010-10-25T00:20:00.001-07:00

Remember, this is only for information. We're not connected to them!

HIRING - Peregrine Semiconductor - RF Modeling Device Engineer

Click Here to Apply: https://home.eease.adp.com/recruit/?id=531727

Job Description:
This position is responsible for:
Member of team responsible for device modeling of Peregrine’s patented high-performance UltraCMOSTM silicon-on-sapphire CMOS process and packaging technology. The candidate will work closely with modeling engineers and CAD to support our design groups and external foundry customers.

Roles & Responsibilities will include:
• Responsible for modeling of passive components.
• Responsible for parasitic analysis of RF active components and BEOL.
• Model extraction for components on-wafer, modules, and packages.
• Manufacturing data analysis to develop statistical and corner models.
• Test chip DOE development, layout, and measurement.
• Provide guidance to design teams on best practice.

Qualifications:

Minimum Requirements:
• Ph.D. in Physics or Electrical Engineering (MS okay with demonstrated experience)
• Understanding of RF device performance metrics
• Experience using SPICE like circuit simulators to develop sub-circuit models.
• Experience using EM simulators (HFSS, Momentum, etc.) to study device performance.
• Demonstrated ability to extract models from measured data.
• Demonstrated problem solving skills.

The following traits are highly valued:
• Strong programming background and ability to develop automation scripts.
• Experience with Matlab, ICCAP, or other tool for model extraction.
• Layout optimization for RF applications.
• Experience configuring and automating test equipment.
• Large signal RF device characterization.

[mos-ak] MOS-AK/GSA Seville Workshop Press Release

2010-10-15T07:29:00.000-07:00

Press release:
"MOS-AK/GSA Modeling Working Group Holds Workshop in Seville"
can be found on the GSA site at
http://www.gsaglobal.org/news/article.asp?article=2010/1014

Modelling people wanted...

2010-10-15T00:11:00.001-07:00

I copy from LinkedIn:

Looking for PhD/ MS candidates in device physics , modelling back ground for one of the Semiconductor research and development centre at Bangalore .

see more...

Accurately simulate an LED

2010-10-13T00:23:00.000-07:00

Accurately simulate an LED: " View as PDF Read More Design IdeasSolid-state-lighting applicatio..."

SEMI urges less bureaucratic approach to EU research funding

2010-10-13T00:22:00.000-07:00

SEMI urges less bureaucratic approach to EU research funding: "San Jose-based manufacturing organization SEMI is advocating for a simplifica..."

The Nobel Prize in Physics 2010 (graphene)

2010-10-05T05:19:00.000-07:00

The Royal Swedish Academy of Sciences has decided to award the Nobel Prize in Physics for 2010 to Andre Geim and Konstantin Novoselov, both at University of Manchester, UK “for groundbreaking experiments regarding the two-dimensional material graphene”.

Andre Geim, Dutch citizen. Born 1958 in Sochi, Russia. Ph.D. 1987 from Institute of Solid State Physics, Russian Academy of Sciences, Chernogolovka, Russia. Director of Manchester Centre for Meso-science & Nanotechnology, Langworthy Professor of Physics and Royal Society 2010 Anniversary Research Professor, University of Manchester, UK.
Konstantin Novoselov, Brittish and Russian citizen. Born 1974 in Nizhny Tagil, Russia. Ph.D. 2004 from Radboud University Nijmegen, The Netherlands. Professor and Royal Society Research Fellow, University of Manchester, UK.

Read the press release...

AWR Announces New PDK for Cree GaN HEMT MMIC Foundry

2010-10-04T23:36:00.000-07:00

The Cree GaN HEMT MMIC process features high power density (4-6 watts/mm) transistors, slot vias, and high reliability (up to 225ºC operating channel temperatures), as well as scalable transistors. [more]