Wednesday, 30 July 2014

Semiconductor Devices Characterization Seminar

Technical Seminars addressing the challenges of CMOS, Power and RF
semiconductor device measurement and modeling 
Agilent and it´s 25 collaborative partners invite you to attend this complimentary technical seminar on characterization and modeling of semiconductor devices. Two tracks in parallel will address the needs for:
  • Small scale silicon industry
  • Power silicon industry and RF Power
Common topics to both Tracks:
  • Live demonstration of GaN device characterization flow: DC I-V characteristic extraction, RF Power measurement, Spice models creation for further usage in design stage.
CMOS Track:
  • Accurate and repeatable on-the-wafer device extraction – Cascade Microtech
  • DC characterization for emerging nano-technologies
  • Flicker Noise and Random Telegraph Noise
  • Spice model libraries optimization for dedicated application
Power & RF Power Track:
  • High Power Devices measurement
  • III-V devices spice model (DynaFET)
  • Nonlinear Component characterization
  • Non-50ohm Load Pull solution – Maury
Where/when:
To obtain the detail agenda of the nearest session, please select one of the locations below.
CountryCityDateMore Information
FRGrenoble18 September 2014Register here
FIHelsinki23 September 2014Register here
DEMunich30 September 2014Register here
DEDresden2 October 2014Register here
CHLausanne14 October 2014Register here
BELeuven16 October 2014Register here
NLEindhoven17 October 2014Register here
SWGoteborg28 October 2014Register here
UKCambridge30 October 2014Register here
FRLes Ulis6 November 2014Register here


 

 

Monday, 28 July 2014

i-MOS version 201407 release

 The i-MOS team has announced new release of the interactive Modeling and On-line Simulation Platform (i-MOS), version 201407. Through the Developer module launched in April, the UMEM model for organic thin film transistors has been integrated with i-MOS for users' evaluations and applications. Another model implemented is the BSIM4 (version 4.0.0), together with model collections from the Predictive Technology Models.  

Any comments and other equerries can be addressed to
Lining Zhang,
PhD i-MOS Project Manager
The Hong Kong University of Science & Technology

Wednesday, 16 July 2014

[SISPAD] Compact Modeling Worksops - Enabling Better Insight of Device Features - Monday, September 8, 2014


 SISPAD Compact Modeling Workshop
 Enabling Better Insight of Device Features 
 Monday, September 8, 2014

 Workshop Program

09:15 - 09:20: Opening 

09:20 - 10:00: J. Takeya (University of Tokyo, Japan): invited Physics of Charge Transport in Organic Field-Effect Transistors
10:00 - 10:40: C. Jungemann (RWTH Aachen University, Germany): invited Validity of Macroscopic Noise Models in the Case of High-Frequency Bipolar Transistors
10:40 - 11:00: break
11:00 - 11:40: N. Goldsman (University of Maryland, USA): invited Key Issues in the Modeling of SiC Electronic Devices
11:40 - 12:10: C. Ma (Hiroshima University, Japan): invited Universal Model of the Negative Bias Temperature Instability (NBTI) Effect for Circuit Aging Simulation

12:10 - 12:30: poster presentations
  • P. X. Tran (International University, Vietnam) A Comprehensive Model for the Changing I-V Characteristics of raphene Transistors 
  • M. Ghittorelli, F. Torricelli, Z. M. Kovacs-Vajna, and L. Calalongo (University of Brescia, Italy) Accurate Modeling of Amorphous Indium-Gallium-Zinc-Oxide TFTs Deposited on Plastic Foil 
  • S. Sato, Y. Omura, and A. Mallik (Kansai University, Japan) Proposal of Simple Channel-Length-Dependent Current Model for Subthreshold Region of Nano-Wire Tunnel FET 
  • H. Miyamoto, H. Zenitani, H. Kikuchihara, H. J. Mattausch, M. Miura-Mattausch, and T. Nakagawa (HU & AIST, Japan) Consistent Compact Modeling of MOSFETs from Bulk to Double-Gate Structures
12:30 - 13:50: lunch

13:50 - 14:30: D. Warning (Creative Chips GmbH, Germany): invited NGSPICE – an Open Platform for Modeling and Simulation
14:30 - 15:00: A. Schaldenbrand (Cadence Design Systems, Japan): invited Benefits of Verilog-A for Behavioral Modeling and Compact Modeling
15:00 - 15:30: P. Lee (Micron Memory Japan, Inc.): invited Compact Model Coalition: World-Wide Model Standardization for an Expanding Industry

15:30 - 15:40: break

15:40 - 16:00: F. Torricelli, M. Ghittorelli, M. Rapisarda, L. Mariucci, S. Jacob, R. Coppard, E. Cantatore, Z. M. Kovacs-Vajna, and L. Colalongo (Unviersity of Brescia, Italy) Analytical Drain Current Model of Both p- and n-Channel OTFTs for Circuit Simulation
16:00 - 16:20: T. Nakagawa, T. Sekigawa, M. Hioki, Y. Ogasahara, H. Koike, H. Zenitani, H. Miyamoto, H. Kikuchihara, H. J. Mattausch, M. Miura-Mattausch, H. Oda, and N. Sugii (AIST, HU, LEAP, Japan) Parameter-Extraction Strategy of Ultra-Thin Silicon and BOX Layer MOSFETs for Low Voltage Applications
16:20 - 16:40: T. Mizoguchi, T. Naito, Y. Kawaguchi, and W. Hatano (Toshiba, Japan) Compact Modeling of GaN-MISFET for Power Applications
16:40 - 17:00: T. Yamamoto and H. Kato (Denso, Japan) Analysis and Modeling of Injection Enhanced Insulated Gate Bipolar Transistor

17:00: Closing