Wednesday, 28 April 2010

POWER/HVMOS Devices Compact Modeling

POWER/HVMOS Devices Compact Modeling
W. Grabinski and T. Gneiting, (Eds.)
1st Edition., 2010, V, 300 p., Hardcover
ISBN: 978-90-481-3045-0

Content Level » Research

Keywords » HV EKV, HV HiSIM,MM20, compact modeling - LDMOS, VDMOS, quasi-saturation, self heating - power, high voltage semiconductor devices

CHAPTER 1: Numerical Power/HV Device Simulations; Oliver Triebl and Tibor Grasser.

CHAPTER 2: HiSIM-HV: A scalable, surface-potential-based compact model for symmetric and asymmetric high-voltage MOSFETs; Hans J. Mattausch, Norio Sadachika, M. Yokomichi, M. Miyake, T. Kajiwara, H. Kikuchihara, U. Feldmann, and M. Miura-Mattausch.

CHAPTER 3: MM20 HVMOS Model: a surface-potential based LDMOS model for circuit simulation; Annemarie Aarts and Alireza Tajic.

CHAPTER 4: Practical HV DMOS modeling using HVEKV; Yogesh Singh Chauhan, Francois Krummenacher and Adrian Mihai Ionescu.

CHAPTER 5: Power Devices; Andrzej Napieralski, Malgorzata Napieralska and Lukasz Starzak.

CHAPTER 6: Distributed modeling approach applied to the IGBT; Patrick Austin and Jean-Louis Sanchez.

CHAPTER 7: Web Based Modeling Tools; Andrzej Napieralski, Lukasz Starzak, Bartlomiej Swiercz and Mariusz Zubert.

Tuesday, 27 April 2010

[mos-ak] MOS-AK/GSA Rome Workshop Press Release

MOS-AK/GSA Modeling Working Group Holds Workshop in Rome
Academic and Industrial Experts Share Their Latest Perspectives on
Compact Modeling and Verilog-A Standardization

in other sources:

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New IEEE EDS Senior Members

My warmest welcome to the new IEEE Senior Members of the EDS in April:

Alberto Adan, Carlos Araujo, M Scott Burroughs, Gerd Hechtfischer, Aaron Ho, Syed Islam, Ioannis Kymissis, Sungjae Lee, Xian Liu, M Madheswaran, Enrique Miranda, Michael Parker, Vijay Reddy, Sean Rommel, Nikita Ryskin, Nayanathara Sattiraju, Keyhan Sinai, Bhaskar Srinivasan, Munehiro Tada, Tsuyoshi Tanaka, Thy Tran, Mingwei Xu, Tetsuo Yamada

Friday, 23 April 2010

[mos-ak] MOS-AK/GSA Rome workshop on-line publications

MOS-AK/GSA Rome workshop on-line publications are available:

I would like to thank all MOS-AK speakers and poster presenters for
sharing their compact modeling competence, R&D experience and
delivering valuable MOS-AK presentations. I am sure, that our modeling
event in Rome was beneficial to all MOS-AK Workshop attendees.

Organization of our modeling event would not be possible without our
generous sponsor: Agilent Technologies, Micron and Micron Foundation
as well as the IEEE EDS, technical co-sponsor. I also would like to
personally acknowledge local organizers, in particular, Professors
Fernanda Irrera and Marco Balucani for their dedication, commitment.
My very special 'thank you' goes to Angela Gatto and Paolo Nenzi not
only for providing smooth workshop logistics.

I hope, we would have a next chance to meet all of you and your
academic and industrial partners at future MOS-AK/GSA modeling events
(listed below).

-- with regards - WG (for the MOS-AK/GSA)
* London: May 18-19,
* Tarragona: Jun.30-Jul.1
* Wroclaw: June 24-26
* Seville: Sept. 17
* San Francisco: Dec'10

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Tuesday, 20 April 2010

3rd International Workshop on Compact Thin-Film Transistor Modeling (C-TFT)

The 3rd International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation (C-TFT) will be held in Tarragona on July 2 2010.

The C-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London.

A partial list of the areas of interest includes:

- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
Other details:
Prospective authors are invited to submit an abstract of up to 500-word to:

Important dates:

- Deadline for abstract submission: May 7, 2010
- Notification of acceptance: May 21, 2010
- Camera-ready version: Jun 18, 2010

This event will be held in coordination with the Training Courses on Compact Modeling (June 30-July 1) and the Graduate Student Meeting on Electronic Engineering (June 28-29).

Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

Training Courses on Compact Modeling: June 30-July 1 2010

The first edition of the Training Courses on Compact Modeling (TCCM) will consist of a set of lectures addressing relevant topics in the compact modeling of advanced electron devices. Most of the courses will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Courses on Compact Modeling will be held in Tarragona (Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).

The Training Courses on Compact Modeling are sponsored by the FP7 “COMON” IAPP Project and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.

The Training Courses on Compact Modeling will be especially suited to researchers from both industry and academia working on electron device modeling, circuit and systems design and electronic design automated tools. In particular, the courses will be very interesting and useful to students working on these topics.

The General Chair Person is Prof. Benjamin IƱiguez, Universitat Rovira i Virgili, Tarragona, Spain.

The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee.


A total of 10 lectures will be conducted. Tthe final programme, with the timetable, will be available soon.
1. Tibor Grasser (TU-Wien) - Transport modeling
2. Tor A Fjeldly (UniK, Norway) - Analytical 2D and 3D electrostatic modeling
3. Jamal Deen (McMaster University, Canada) - Noise modeling
4. Benjamin Iniguez (URV, Spain) - Analytical small-signal modeling
5. Ilcho Angelov (Chalmers University, Sweden) - High frequency device modeling
6. Renaud Gillon (On Semiconductor, Belgium) - Electro-thermal and reliability modeling
7. Sorin Cristoloveanu (MINATEC and LETI, France) - Electrical characterization of SOI and Multi-Gate MOSFETs
8. Asen Asenov (University of Glasgow) - Statistical variability and corresponding compact model strategies
9. Kiyoh Itoh (Hitachi, Japan) - "Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs"
10. Wladek Grabinski - "GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization"

Tuesday, 6 April 2010

The Semiconductor Industry’s Nanoelectronics Research Initiative: Motivation and Challenges

Part-2 in the IEEE SCV Electron Devices Society (EDS) "Semiconductor Roadmap and Beyond" series.

Speaker: Dr. Jeffrey Welser, Director, SRC Nanoelectronics Research Initiative

Time: TUESDAY, Apr 13, 2010 6:00 PM - Pizza , 6:15 PM – Lecture

Cost: Free
Location: National Semiconductor
, Building E1, Conference Center ,
2900 Semiconductor Drive , Santa Clara , CA 95051
See the NSC Building location map and directions

Contact: Sandeep Bahl

Web link:

Alliance CAD System

Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor:

This project may now be found at